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MC68HC908GT16 MC68HC908GT8
Data Sheet
M68HC08 Microcontrollers
MC68HC908GT16 Rev. 3 09/2004
freescale.com
MC68HC908GT16 MC68HC908GT8
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History (Sheet 1 of 2)
Date March, 2002 Revision Level N/A Original release 7.2 Features -- Corrected third bulleted item to reflect 4 percent variability Figure 15-1. Forced Monitor Mode (Low) -- Reworked for clarity Figure 15-2. Forced Monitor Mode (High) -- Reworked for clarity May, 2002 Figure 15-3. Standard Monitor Mode -- Reworked for clarity 1.0 Table 15-1. Monitor Mode Signal Requirements and Options -- Reworked for clarity Figure 12-4. Port A I/O Circuit -- Reworked to correct pullup resistor Figure 12-11. Port C I/O Circuit -- Reworked to correct pullup resistor Figure 12-15. Port D I/O Circuit -- Reworked to correct pullup resistor Description Page Number(s) N/A 75 211 211 212 214 143 148 151
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc., 2004. All rights reserved. MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 3
Revision History
Revision History (Sheet 2 of 2)
Date Revision Level Description Figure 2-2. Control, Status, and Data Registers -- Corrected ESCI arbiter data register (SCIADAT) to reflect read-only status June, 2002 2.0 Figure 14-19. ESCI Arbiter Control Register (SCIACTL) -- Corrected address location designator from $0018 to $000A Figure 14-20. ESCI Arbiter Data Register (SCIADAT) -- Corrected address location designator from $0019 to $000B Reformatted to meet current publications standards 1.5.6 ADC Reference Pins (VREFH and VREFL) -- Corrected connections 2.6.3 FLASH Page Erase Operation -- Updated procedure 2.6.4 FLASH Mass Erase Operation -- Updated procedure 2.6.5 FLASH Program/Read Operation -- Updated procedure 2.6.6 FLASH Block Protection -- Description updated for clarity 3.3.5 Conversion -- Updated for clarity 3.6.3 ADC Voltage Reference High Pin (VREFH) -- Corrected connections 3.6.4 ADC Voltage Reference Low Pin (VREFL) -- Corrected connections 3.7.1 ADC Status and Control Register -- Updated description of the COCO bit Chapter 4 Configuration Register (CONFIG) -- Updated COP tmeout selections Chapter 4 Configuration Register (CONFIG) -- Updted SSREC bit usage Chapter 5 Computer Operating Properly (COP) Module -- Updated timeout selections Figure 5-1. COP Block Diagram -- Updated illustration for clarity Table 6-1. Instruction Set Summary -- Updated definitions for STOP and WAIT September, 2004 3.0 Figure 7-9. Code Example for Switching Clock Sources -- Replaced example code Figure 7-10. Code Example for Enabling the Clock Monitor -- Replaced example code Figure 14-18. ESCI Prescaler Register (SCPSC) -- Corrected address location Chapter 15 System Integration Module (SIM) -- Clarified SIM features and functionality 15.7.2 SIM Reset Status Register -- Clarified SRSR operation Table 19-1. Monitor Mode Signal Requirements and Options -- Reworked 19.2.1 Functional Description -- Corrected Break description 19.3 Monitor Module (MON) -- Reworked Chapter 20 Electrical Specifications -- Revised/added tables: 20.5 5.0-V DC Electrical Characteristics 20.6 3.0-V DC Electrical Characteristics 20.7 Supply Current Characteristics 20.8 5-V Control Timing 20.9 3-V Control Timing 20.20 Memory Characteristics -- Updated memory table Chapter 20 Electrical Specifications -- Added figures: Figure 20-1. RST and IRQ Timing Figure 20-2. RST and IRQ Timing Page Number(s) 50 170 171 Throughout 24 39 40 41 43 50 51 51 52 55, 57 58 60 59 68 87 88 170 177, 180, 181, 182 192 245 235, 238 241 255 256 257 258 258 271 258 258
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 4 Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 4 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chapter 5 Computer Operating Properly (COP) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Chapter 6 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Chapter 7 Internal Clock Generator (ICG) Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Chapter 8 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chapter 10 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Chapter 11 Low-Power Modes (MODES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Chapter 12 Input/Output (I/O) Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Chapter 13 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Chapter 14 Enhanced Serial Communications Interface (ESCI) Module . . . . . . . . . . . . . 147 Chapter 15 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Chapter 16 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Chapter 17 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Chapter 18 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Chapter 20 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 273
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 5
List of Chapters
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 6 Freescale Semiconductor
Table of Contents
Chapter 1 General Description
1.1 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Features of the MC68HC908GT16/MC68HC908GT8 . . . . . . . . . . . . . . . . . . . . . Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Pins (VDD and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Pins (PTE4/OSC1 and PTE3/OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Pin (RST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC and ICG Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Reference Pins (VREFH and VREFL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Input/Output (I/O) Pins (PTA7/KBD7-PTA0/KBD0) . . . . . . . . . . . . . . . . . . . . . . . . . Port B I/O Pins (PTB7/AD7-PTB0/AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C I/O Pins (PTC6-PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D I/O Pins (PTD7/T2CH1-PTD0/SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E I/O Pins (PTE4-PTE2, PTE1/RxD, and PTE0/TxD) . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 20 21 22 23 23 24 24 24 24 24 25 25 25 25 25
Chapter 2 Memory
2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 2.6.8 2.6.9 2.6.10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output (I/O) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICG User Trim Registers (ICGTR5 and ICGTR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 27 38 38 38 39 39 40 41 43 43 44 45 45
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 7
Table of Contents
Chapter 3 Analog-to-Digital Converter (ADC)
3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.4 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.7 3.7.1 3.7.2 3.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Voltage Reference High Pin (VREFH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Voltage In (VADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 47 47 47 49 49 50 50 50 50 50 50 51 51 51 51 51 51 52 52 52 53 54
Chapter 4 Configuration Register (CONFIG)
4.1 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 5 Computer Operating Properly (COP) Module
5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.4 5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 60 60 60 60 60 60 61 61 61 61 61
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 8 Freescale Semiconductor
5.6 5.7 5.7.1 5.7.2 5.8
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61 61 61 62 62
Chapter 6 Central Processor Unit (CPU)
6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 63 63 64 64 65 65 66 67 67 67 67 67 68 73
Chapter 7 Internal Clock Generator (ICG) Module)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 Clock Enable Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Internal Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.1 Digitally Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.2 Modulo N Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.3 Frequency Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.4 Digital Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3 External Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3.1 External Oscillator Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3.2 External Clock Input Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.4 Clock Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.4.1 Clock Monitor Reference Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.4.2 Internal Clock Activity Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.4.3 External Clock Activity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.5 Clock Selection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.5.1 Clock Selection Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.5.2 Clock Switching Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 75 75 78 78 79 79 80 80 81 81 82 82 82 84 84 85 86 86
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7.4 Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Switching Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 Enabling the Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3 Using Clock Monitor Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.4 Quantization Error in DCO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.4.1 Digitally Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.4.2 Binary Weighted Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.4.3 Variable-Delay Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.4.4 Ring Oscillator Fine-Adjust Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.5 Switching Internal Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6 Nominal Frequency Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6.1 Settling to Within 15 Percent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6.2 Settling to Within 5 Percent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6.3 Total Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.7 Trimming Frequency on the Internal Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.1 External Clock Enable (EXTCLKEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.2 External Crystal Enable (EXTXTALEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.3 Slow External Clock (EXTSLOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.4 Oscillator Enable In Stop (OSCENINSTOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.1 ICG Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.2 ICG Multiplier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.3 ICG Trim Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.4 ICG DCO Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.5 ICG DCO Stage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86 87 87 88 88 89 89 89 90 90 90 91 91 91 92 92 92 93 93 93 93 94 94 94 96 97 98 98 98
Chapter 8 External Interrupt (IRQ)
8.1 8.2 8.3 8.4 8.5 8.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 9 Keyboard Interrupt Module (KBI)
9.1 9.2 9.3 9.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 105 105 108
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9.5 9.5.1 9.5.2 9.6 9.7 9.7.1 9.7.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108 108 109 109 109 109 110
Chapter 10 Low-Voltage Inhibit (LVI)
10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.5 10.6 10.6.1 10.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 111 111 112 112 112 113 113 113 113 113 114
Chapter 11 Low-Power Modes (MODES)
11.1 11.1.1 11.1.2 11.2 11.2.1 11.2.2 11.3 11.3.1 11.3.2 11.4 11.4.1 11.4.2 11.5 11.5.1 11.5.2 11.6 11.6.1 11.6.2 11.7 11.7.1 11.7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Clock Generator Module (ICG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Computer Operating Properly Module (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Module (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 115 115 115 115 115 115 115 116 116 116 116 116 116 116 117 117 117 117 117 117
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11.8 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.9 Low-Voltage Inhibit Module (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.10 Enhanced Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.11 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.12 Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.12.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.14 Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.15 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
117 117 117 117 117 118 118 118 118 118 118 118 118 118 119 119 119 119 119 120
Chapter 12 Input/Output (I/O) Ports (PORTS)
12.1 12.2 12.2.1 12.2.2 12.2.3 12.3 12.3.1 12.3.2 12.4 12.4.1 12.4.2 12.4.3 12.5 12.5.1 12.5.2 12.5.3 12.6 12.6.1 12.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 124 124 124 125 126 126 126 127 128 128 129 130 130 131 132 132 133 133
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Chapter 13 Resets and Interrupts
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3.3 Low-Voltage Inhibit Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3.4 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.4 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.1 Software Interrupt (SWI) Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.2 Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.3 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.4 Internal Clock Generator (ICG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.5 Timer Interface Module 1 (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.6 Timer Interface Module 2 (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.7 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.8 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.9 KBD0-KBD7 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.10 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2.11 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 135 135 135 135 136 136 137 137 137 137 138 138 141 141 142 142 142 142 142 142 143 143 143 144 144 145 145 145
Chapter 14 Enhanced Serial Communications Interface (ESCI) Module
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 147 147 149 150 151 151 151 152 152 153 153
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14.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.6 ESCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.7.1 PTE0/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.7.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.8.1 ESCI Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.8.2 ESCI Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.8.3 ESCI Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.8.4 ESCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.8.5 ESCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.8.6 ESCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.8.7 ESCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.8.8 ESCI Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.9 ESCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.9.1 ESCI Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.9.2 ESCI Arbiter Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.9.3 Bit Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.9.4 Arbitration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Chapter 15 System Integration Module (SIM)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2.6 Monitor Mode Entry Module Reset (MODRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 179 179 180 180 180 180 181 181 182 182 183 183 183
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15.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.1.3 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
183 183 183 183 184 184 185 186 186 188 188 188 189 189 190 191 191 192 193
Chapter 16 Serial Peripheral Interface (SPI) Module
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.9 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.9.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.9.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.10 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.11 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.11.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.11.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 195 195 198 198 199 199 199 200 201 203 204 204 205 207 208 208 208 208 208 209 209 209
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Table of Contents
16.11.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.11.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
209 210 211 211 212 214
Chapter 17 Timebase Module (TBM)
17.1 17.2 17.3 17.4 17.5 17.6 17.6.1 17.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timebase Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 215 215 216 217 218 218 218
Chapter 18 Timer Interface Module (TIM)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 221 221 221 223 223 224 224 224 225 225 226 226 227 227 227 228 228 228 228 229 230 231 231 234
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Chapter 19 Development Support
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.1.2 TIM1 and TIM2 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.2 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.2.3 SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.2.4 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 235 235 238 238 238 238 239 239 240 240 241 241 245 246 246 247 247 247 247 250
Chapter 20 Electrical Specifications
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5 5.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.6 3.0-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.8 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.9 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.10 Internal Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.11 External Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.12 Trimmed Accuracy of the Internal Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.12.1 2.7-Volt to 3.3-Volt Trimmed Internal Clock Generator Characteristics . . . . . . . . . . . . . . . 20.12.2 4.5-Volt to 5.5-Volt Trimmed Internal Clock Generator Characteristics . . . . . . . . . . . . . . . 20.13 Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.14 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.15 Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.16 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 253 254 254 255 256 257 258 258 259 259 260 260 260 261 263 265 266
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 17
Table of Contents
20.17 20.18 20.19 20.20
5.0-V SPI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0-V SPI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
267 268 271 271
Chapter 21 Ordering Information and Mechanical Specifications
21.1 21.2 21.3 21.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-Pin Shrink Dual in-Line Package (SDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 273 274 275
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 18 Freescale Semiconductor
Chapter 1 General Description
1.1 Introduction
The MC68HC908GT16 and the MC68HC908GT8 are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. All references to the MC68HC908GT16 in this data book apply equally to the MC68HC908GT8, unless otherwise stated.
1.2 Features
For convenience, features have been organized to reflect: * Standard features of the MC68HC908GT16/MC68HC908GT8 * Features of the CPU08
1.2.1 Standard Features of the MC68HC908GT16/MC68HC908GT8
* * * * High-performance M68HC08 architecture optimized for C-compilers Fully upward-compatible object code with M6805, M146805, and M68HC05 Families 8-MHz internal bus frequency Internal oscillator requiring no external components: - Software selectable bus frequencies - 25 percent accuracy with trim capability to 4 percent - Clock monitor - Option to allow use of external clock source or external crystal/ceramic resonator FLASH program memory security(1) On-chip programming firmware for use with host personal computer which does not require high voltage for entry In-system programming (ISP) System protection features: - Optional computer operating properly (COP) reset - Low-voltage detection with optional reset and selectable trip points for 3.0-V and 5.0-V operation - Illegal opcode detection with reset - Illegal address detection with reset Low-power design; fully static with stop and wait modes Standard low-power modes of operation: - Wait mode - Stop mode
* * * *
* *
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 19
General Description
* * * * * * * * * * *
* * * *
* * *
*
*
Master reset pin and power-on reset (POR) 16 Kbytes of on-chip 100k cycle write/erase capable FLASH memory (8 Kbytes on MC68HC908GT8) 512 bytes of on-chip random-access memory (RAM) 720 bytes of FLASH programming routines ROM Serial peripheral interface module (SPI) Serial communications interface module (SCI) Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel 8-channel, 8-bit successive approximation analog-to-digital converter (ADC) Break module (BRK) to allow single breakpoint setting during in-circuit debugging Internal pullups on IRQ and RST to reduce customer system cost Up to 36 general-purpose input/output (I/O) pins, including: - 28 shared-function I/O pins - Six or eight dedicated I/O pins, depending on package choice Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis. During output mode, pullups are disengaged. High current 10-mA sink/10-mA source capability on all port pins Higher current 20-mA sink/source capability on PTC0-PTC4 Timebase module with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source during stop mode for periodic wakeup from stop using an external 32-kHz crystal or internal oscillator User selection of having the oscillator enabled or disabled during stop mode 8-bit keyboard wakeup port Available packages: - 42-pin shrink dual in-line package (SDIP) - 44-pin quad flat pack (QFP) Specific features of the MC68HC908GT16 in 42-pin SDIP are: - Port C is only 5 bits: PTC0-PTC4 - Port D is 8 bits: PTD0-PTD7; dual 2-channel TIM modules Specific features of the MC68HC908GT16 in 44-pin QFP are: - Port C is 7 bits: PTC0-PTC6 - Port D is 8 bits: PTD0-PTD7; dual 2-channel TIM modules
1.2.2 Features of the CPU08
Features of the CPU08 include: * Enhanced HC05 programming model * Extensive loop control functions * 16 addressing modes (eight more than the HC05) * 16-bit index register and stack pointer * Memory-to-memory data transfers * Fast 8 x 8 multiply instruction * Fast 16/8 divide instruction * Binary-coded decimal (BCD) instructions * Optimization for controller applications * Efficient C language support
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 20 Freescale Semiconductor
MCU Block Diagram
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908GT16.
INTERNAL BUS PORTA M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(3) SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA SERIAL PERIPHERAL INTERFACE MODULE PORTB DDRB PTA7/KBD7- PTA0/KBD0(1) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1)(2) PTC3(1)(2) PTC2(1)(2) PTC1(1)(2) PTC0(1)(2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE2 PTE1/RxD PTE0/TxD
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH MC68HC908GT16 -- 15,872 BYTES MC68HC908GT8 -- 7,680 BYTES USER RAM -- 512 BYTES MONITOR ROM -- 304 BYTES FLASH PROGRAMMING ROUTINES ROM -- 720 BYTES USER FLASH VECTOR SPACE -- 36 BYTES
PTE4/OSC1 PTE3/OSC2
INTERNAL CLOCK GENERATOR MODULE
IRQ(3) VREFH VREFL
MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE
PORTE
MONITOR MODULE DDRE
PORTD
DDRD
PORTC
DDRC
SECURITY MODULE
POWER
MONITOR MODE ENTRY MODULE
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
Figure 1-1. MCU Block Diagram
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 21
General Description
1.4 Pin Assignments
PTA7/KBD7 PTA6/KBD6 PTA5/KBD5 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 VREFL (ADC) VREFH (ADC) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTD7/T2CH1 PTD6/T2CH0 PTD5/T1CH1
VDDA (ADC/ICG) VSSA (ADC/ICG) PTE2 PTE3/OSC2 PTE4/OSC1 RST PTC0 PTC1 PTC2 PTC3 PTC4 PTE0/TxD PTE1/RxD IRQ PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK VSS VDD PTD4/T1CH0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Pins Not Available on 42-Pin Package PTC5 PTC6
Internal Connection Connected to ground Connected to ground
Figure 1-2. 42-Pin SDIP Pin Assignments
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 22 Freescale Semiconductor
Pin Functions
PTE4/OSC1 PTE3/OSC2
PTA5/KBD5
PTA4/KBD4
PTA7/KBD7
PTA6/KBD6
44
43
42
41
40
39
38
37
36
35
PTA3/KBD3
RST 1 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTE0/TxD PTE1/RxD IRQ 11 2 3 4 5 6 7 8 9 10 12 13
34
PTA2/KBD2
PTE2
VDDA
VSSA
33 32 31 30 29
PTA1/KBD1 PTA0/KBD0 VREFL VREFH PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2
28 27 26 25 24 21 14 15 16 17 18 19 20 22 23
PTB1/AD1
PTD3/SPSCK
PTD4/T1CH0
PTD5/T1CH1
PTD6/T2CH0
Figure 1-3. 44-Pin QFP Pin Assignments
1.5 Pin Functions
Descriptions of the pin functions are provided here.
1.5.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 23
PTD7/T2CH1
PTD1/MISO
PTD2/MOSI
PTB0/AD0
PTD0/SS
VSS
VDD
General Description
MCU VDD VSS
C1 0.1 F
+ C2
VDD Note: Component values shown represent typical applications.
Figure 1-4. Power Supply Bypassing
1.5.2 Oscillator Pins (PTE4/OSC1 and PTE3/OSC2)
PTE4/OSC1 and PTE3/OSC2 are general-purpose, bidirectional I/O port pins. These pins can also be programmed to be the connections for an external crystal, resonator or clock circuit. See Chapter 7 Internal Clock Generator (ICG) Module).
1.5.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin contains an internal pullup resistor. See Chapter 15 System Integration Module (SIM).
1.5.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Chapter 8 External Interrupt (IRQ).
1.5.5 ADC and ICG Power Supply Pins (VDDA and VSSA)
VDDA and VSSA are the power supply pins for the analog-to-digital converter (ADC) and the internal clock generator (ICG). Connect the VDDA pin to the same voltage potential as VDD, and the VSSA pin to the same voltage potential as VSS. Decoupling of these pins should be as per the digital supply. See Chapter 3 Analog-to-Digital Converter (ADC) and Chapter 7 Internal Clock Generator (ICG) Module).
1.5.6 ADC Reference Pins (VREFH and VREFL)
VREFH and VREFL are the reference voltage pins for the analog-to-digital converter (ADC). VREFH is the high reference supply for the ADC and should be filtered. VREFH must be connected to the same voltage potential as the analog supply pin, VDDA. VREFL is the low reference supply for the ADC and should be externally filtered. VREFL must be connected to the same voltage potential as the analog supply pin VSSA. See Chapter 3 Analog-to-Digital Converter (ADC).
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 24 Freescale Semiconductor
Pin Functions
1.5.7 Port A Input/Output (I/O) Pins (PTA7/KBD7-PTA0/KBD0)
PTA7-PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be programmed to serve as keyboard interrupt pins. See Chapter 12 Input/Output (I/O) Ports (PORTS) and Chapter 9 Keyboard Interrupt Module (KBI). These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.8 Port B I/O Pins (PTB7/AD7-PTB0/AD0)
PTB7-PTB0 are general-purpose, bidirectional I/O port pins that can also be used for analog-to-digital converter (ADC) inputs. See Chapter 12 Input/Output (I/O) Ports (PORTS) and Chapter 3 Analog-to-Digital Converter (ADC).
1.5.9 Port C I/O Pins (PTC6-PTC0)
PTC6-PTC0 are general-purpose, bidirectional I/O port pins. PTC0-PTC4 have higher current sink/source capability. PTC5 and PTC6 are only available on the 44-pin QFP package. These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. See Chapter 12 Input/Output (I/O) Ports (PORTS).
1.5.10 Port D I/O Pins (PTD7/T2CH1-PTD0/SS)
PTD7-PTD0 are special-function, bidirectional I/O port pins. PTD0-PTD3 can be programmed to be serial peripheral interface (SPI) pins, while PTD4-PTD7 can be individually programmed to be timer interface module (TIM1 and TIM2) pins. See Chapter 18 Timer Interface Module (TIM), Chapter 16 Serial Peripheral Interface (SPI) Module, and Chapter 12 Input/Output (I/O) Ports (PORTS). These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis.
1.5.11 Port E I/O Pins (PTE4-PTE2, PTE1/RxD, and PTE0/TxD)
PTE0-PTE4 are general-purpose, bidirectional I/O port pins. PTE0-PTE1 can also be programmed to be serial communications interface (SCI) pins. See Chapter 14 Enhanced Serial Communications Interface (ESCI) Module and Chapter 12 Input/Output (I/O) Ports (PORTS). PTE3 and PTE4 can also be programmed to be clock or oscillator pins. See Chapter 4 Configuration Register (CONFIG) and Chapter 12 Input/Output (I/O) Ports (PORTS). NOTE Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports do not require termination, termination is recommended to reduce the possibility of static damage.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 25
General Description
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 26 Freescale Semiconductor
Chapter 2 Memory
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: * User FLASH memory: - MC68HC908GT16 -- 15,872 bytes - MC68HC908GT8 -- 7,680 bytes * 512 bytes of random-access memory (RAM) * 720 bytes of FLASH programming routines read-only memory (ROM) * 36 bytes of user-defined vectors * 304 bytes of monitor ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R.
2.4 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000-$003F. Additional I/O registers have these addresses: * $FE00; SIM break status register, SBSR * $FE01; SIM reset status register, SRSR * $FE02; reserved, SUBAR * $FE03; SIM break flag control register, SBFCR * $FE04; interrupt status register 1, INT1 * $FE05; interrupt status register 2, INT2 * $FE06; interrupt status register 3, INT3 * $FE07; reserved * $FE08; FLASH control register, FLCR * $FE09; break address register high, BRKH * $FE0A; break address register low, BRKL * $FE0B; break status and control register, BRKSCR
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 27
Memory
* * * * *
$FE0C; LVI status register, LVISR $FF7E; FLASH block protect register, FLBPR $FF80; ICG user trim register 5V ICGTR5 $FF81; ICG user trim register 3V ICGTR3 $FFFF; COP control register, COPCTL
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
$0000 $003F $0040 $023F $0240 $1B4F $1B50 $1E1F $1E20 $BFFF $C000 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B SIM BREAK STATUS REGISTER (SBSR) SIM RESET STATUS REGISTER (SRSR) RESERVED (SUBAR) SIM BREAK FLAG CONTROL REGISTER (SBFCR) INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER 2 (INT2) INTERRUPT STATUS REGISTER 3 (INT3) RESERVED FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) Figure is continued on the next page FLASH MEMORY MC68HC908GT16 15,872 BYTES RESERVED(1) FLASH MEMORY MC68HC908GT8 7,680 BYTES 1. Inadvertent access to these locations will not cause an illegal address reset. $C000 $DFFF $E000 $FDFF UNIMPLEMENTED 41,440 BYTES FLASH PROGRAMMING ROUTINES ROM 720 BYTES UNIMPLEMENTED 6416 BYTES RAM 512 BYTES I/O REGISTERS 64 BYTES
Figure 2-1. Memory Map
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 28 Freescale Semiconductor
Input/Output (I/O) Section $FE0C $FE0D $FE0F $FE10 $FE1F $FE20 $FF4F $FF50 $FF7D $FF7E $FF7F $FF80 $FF81 $FF82 $FFDB $FFDC $FFFF(2) FLASH VECTORS 36 BYTES UNIMPLEMENTED 90 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) UNIMPLEMENTED 1 BYTE ICG USER TRIM REGISTER 5V (ICGTR5) ICG USER TRIM REGISTER 3V (ICGTR3) UNIMPLEMENTED 46 BYTES MONITOR ROM 304 BYTES UNIMPLEMENTED 16 BYTES RESERVED FOR COMPATIBILITY WITH MONITOR CODE FOR A-FAMILY PART UNIMPLEMENTED 3 BYTES LVI STATUS REGISTER (LVISR)
2. $FFF6-$FFFD reserved for eight security bytes
Figure 2-1. Memory Map (Continued)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 29
Memory Addr. $0000 Register Name Port A Data Register Read: (PTA) Write: See page 124. Reset: Port B Data Register Read: (PTB) Write: See page 126. Reset: Port C Data Register Read: (PTC) Write: See page 128. Reset: Port D Data Register ( Read: PTD) Write: See page 130. Reset: Data Direction Register A Read: (DDRA) Write: See page 124. Reset: Data Direction Register B Read: (DDRB) Write: See page 126. Reset: Data Direction Register C Read: (DDRC) Write: See page 128. Reset: Data Direction Register D Read: (DDRD) Write: See page 131. Reset: Port E Data Register Read: (PTE) Write: See page 133. Reset: ESCI Prescaler Register Read: (SCPSC) Write: See page 170. Reset: ESCI Arbiter Control Read: Register (SCIACTL) Write: See page 174. Reset: ESCI Arbiter Data Read: Register (SCIADAT) Write: See page 175. Reset: Data Direction Register E Read: (DDRE) Write: See page 134. Reset: Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
$0002
Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset DDRA7 0 DDRB7 0 0 0 DDRD7 0 0 DDRA6 0 DDRB6 0 DDRC6 0 DDRD6 0 0 DDRA5 0 DDRB5 0 DDRC5 0 DDRD5 0 0 DDRA4 0 DDRB4 0 DDRC4 0 DDRD4 0 PTE4 DDRA3 0 DDRB3 0 DDRC3 0 DDRD3 0 PTE3 DDRA2 0 DDRB2 0 DDRC2 0 DDRD2 0 PTE2 DDRA1 0 DDRB1 0 DDRC1 0 DDRD1 0 PTE1 DDRA0 0 DDRB0 0 DDRC0 0 DDRD0 0 PTE0
$0004
$0005
$0006
$0007
$0008
Unaffected by reset PDS2 0 AM1 0 ARD7 0 0 0 PDS1 0 ALOST 0 ARD6 0 0 0 = Unimplemented PDS0 0 AM0 0 ARD5 0 0 0 PSSB4 0 ACLK 0 ARD4 0 DDRE4 0 R = Reserved PSSB3 0 AFIN 0 ARD3 0 DDRE3 0 PSSB2 0 ARUN 0 ARD2 0 DDRE2 0 U = Unaffected PSSB1 0 AOVFL 0 ARD1 0 DDRE1 0 PSSB0 0 ARD8 0 ARD0 0 DDRE0 0
$0009
$000A
$000B
$000C
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 30 Freescale Semiconductor
Input/Output (I/O) Section Addr. $000D Register Name Bit 7 6 PTAPUE6 0 PTCPUE6 0 PTDPUE6 0 R 0 ERRIE 0 R6 T6 5 PTAPUE5 0 PTCPUE5 0 PTDPUE5 0 SPMSTR 1 OVRF 0 R5 T5 4 PTAPUE4 0 PTCPUE4 0 PTDPUE4 0 CPOL 0 MODF 0 R4 T4 3 PTAPUE3 0 PTCPUE3 0 PTDPUE3 0 CPHA 1 SPTE 1 R3 T3 2 PTAPUE2 0 PTCPUE2 0 PTDPUE2 0 SPWOM 0 MODFEN 0 R2 T2 1 PTAPUE1 0 PTCPUE1 0 PTDPUE1 0 SPE 0 SPR1 0 R1 T1 Bit 0 PTAPUE0 0 PTCPUE0 0 PTDPUE0 0 SPTIE 0 SPR0 0 R0 T0
Port A Input Pullup Enable Read: PTAPUE7 Register (PTAPUE) Write: See page 125. Reset: 0 Port C Input Pullup Enable Read: Register (PTCPUE) Write: See page 129. Reset: 0 0
$000E
$000F
Port D Input Pullup Enable Read: PTDPUE7 Register (PTDPUE) Write: See page 132. Reset: 0 SPI Control Register Read: (SPCR) Write: See page 211. Reset: SPI Status and Control Read: Register (SPSCR) Write: See page 212. Reset: SPI Data Register Read: (SPDR) Write: See page 214. Reset: ESCI Control Register 1 Read: (SCC1) Write: See page 161. Reset: ESCI Control Register 2 Read: (SCC2) Write: See page 163. Reset: ESCI Control Register 3 Read: (SCC3) Write: See page 165. Reset: ESCI Status Register 1 Read: (SCS1) Write: See page 166. Reset: ESCI Status Register 2 Read: (SCS2) Write: See page 168. Reset: ESCI Data Register Read: (SCDR) Write: See page 169. Reset: ESCI Baud Rate Register Read: (SCBR) Write: See page 169. Reset: SPRIE 0 SPRF 0 R7 T7
$0010
$0011
$0012
Unaffected by reset LOOPS 0 SCTIE 0 R8 U SCTE 1 ENSCI 0 TCIE 0 T8 U TC 1 TXINV 0 SCRIE 0 R 0 SCRF 0 M 0 ILIE 0 R 0 IDLE 0 WAKE 0 TE 0 ORIE 0 OR 0 ILTY 0 RE 0 NEIE 0 NF 0 PEN 0 RWU 0 FEIE 0 FE 0 BKF 0 R7 T7 0 R6 T6 0 R5 T5 0 R4 T4 0 R3 T3 0 R2 T2 0 R1 T1 PTY 0 SBK 0 PEIE 0 PE 0 RPF 0 R0 T0
$0013
$0014
$0015
$0016
$0017
$0018
Unaffected by reset SCP1 0 0 = Unimplemented 0 SCP0 0 R = Reserved R 0 SCR2 0 U = Unaffected SCR1 0 SCR0 0
$0019
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 31
Memory Addr. Register Name Keyboard Status Read: and Control Register Write: (INTKBSCR) See page 109. Reset: Keyboard Interrupt Enable Read: Register (INTKBIER) Write: See page 110. Reset: Timebase Module Control Read: Register (TBCR) Write: See page 216. Reset: IRQ Status and Control Read: Register (INTSCR) Write: See page 102. Reset: Configuration Register 2 Read: (CONFIG2) Write: See page 56. Reset: Configuration Register 1 Read: (CONFIG1) Write: See page 56. Reset: Bit 7 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 KBIE7 0 TBIF 0 0 0 R 0 COPRS 0 0 KBIE6 0 TBR2 0 0 0 0 0 KBIE5 0 TBR1 0 0 0 EXTXTALEN 0 LVIRSTD 0 0 KBIE4 0 TBR0 0 0 0 EXT-SLOW 0 0 KBIE3 0 0 TACK 0 IRQF1 0 EXTCLKEN 0 0 KBIE2 0 TBIE 0 0 ACK1 0 0 1 IMASKK 0 KBIE1 0 TBON 0 IMASK1 0 OSCENINSTOP 0 STOP 0 Bit 0 MODEK 0 KBIE0 0 R 0 MODE1 0 R 0 COPD 0
$001A
$001B
$001C
$001D
$001E
0 LVISTOP 0
0 SSREC 0
$001F
LVIPWRD LVI5OR3(1) 0 0
1. One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset). Timer 1 Status and Control Read: Register (T1SC) Write: See page 229. Reset: Timer 1 Counter Read: Register High (T1CNTH) Write: See page 230. Reset: Timer 1 Counter Read: Register Low (T1CNTL) Write: See page 230. Reset: Timer 1 Counter Modulo Read: Register High (T1MODH) Write: See page 231. Reset: Timer 1 Counter Modulo Read: Register Low (T1MODL) Write: See page 231. Reset: TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 0 TRST 0 12 0 4 0 12 1 4 1 MS0A 0 R = Reserved 0 11 0 3 0 11 1 3 1 ELS0B 0 0
$0020
TOIE 0 14 0 6 0 14 1 6 1 CH0IE 0
TSTOP 1 13 0 5 0 13 1 5 1 MS0B 0
PS2 0 10 0 2 0 10 1 2 1 ELS0A 0 U = Unaffected
PS1 0 9 0 1 0 9 1 1 1 TOV0 0
PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0
$0021
$0022
$0023
$0024
Timer 1 Channel 0 Status and Read: $0025 Control Register (T1SC0) Write: See page 231. Reset:
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 32 Freescale Semiconductor
Input/Output (I/O) Section Addr. $0026 Register Name Timer 1 Channel 0 Read: Register High (T1CH0H) Write: See page 234. Reset: Timer 1 Channel 0 Read: Register Low (T1CH0L) Write: See page 234. Reset: Bit 7 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0027
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 0 13 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
Timer 1 Channel 1 Status and Read: $0028 Control Register (T1SC1) Write: See page 232. Reset: $0029 Timer 1 Channel 1 Read: Register High (T1CH1H) Write: See page 234. Reset: Timer 1 Channel 1 Read: Register Low (T1CH1L) Write: See page 234. Reset: Timer 2 Status and Control Read: Register (T2SC) Write: See page 229. Reset: Timer 2 Counter Read: Register High (T2CNTH) Write: See page 230. Reset: Timer 2 Counter Read: Register Low (T2CNTL) Write: See page 230. Reset: Timer 2 Counter Modulo Read: Register High (T2MODH) Write: See page 231. Reset: Timer 2 Counter Modulo Read: Register Low (T2MODL) Write: See page 231. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$002A
Indeterminate after reset TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 TOIE 0 14 0 6 0 14 1 6 1 CH0IE 0 14 TSTOP 1 13 0 5 0 13 1 5 1 MS0B 0 13 0 TRST 0 12 0 4 0 12 1 4 1 MS0A 0 12 0 11 0 3 0 11 1 3 1 ELS0B 0 11 0 PS2 0 10 0 2 0 10 1 2 1 ELS0A 0 10 PS1 0 9 0 1 0 9 1 1 1 TOV0 0 9 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$002B
$002C
$002D
$002E
$002F
Timer 2 Channel 0 Status and Read: $0030 Control Register (T2SC0) Write: See page 231. Reset: $0031 Timer 2 Channel 0 Read: Register High (T2CH0H) Write: See page 234. Reset: Timer 2 Channel 0 Read: Register Low (T2CH0L) Write: See page 234. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0032
Indeterminate after reset = Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 33
Memory Addr. Register Name Bit 7 CH1F 0 0 Bit 15 6 CH1IE 0 14 5 0 0 13 4 MS1A 0 12 3 ELS1B 0 11 2 ELS1A 0 10 1 TOV1 0 9 Bit 0 CH1MAX 0 Bit 8
Timer 2 Channel 1 Status and Read: $0033 Control Register (T2SC1) Write: See page 232. Reset: $0034 Timer 2 Channel 1 Read: Register High (T2CH1H) Write: See page 234. Reset: Timer 2 Channel 1 Read: Register Low (T2CH1L) Write: See page 234. Reset: ICG Control Register Read: (ICGCR) Write: See page 96. Reset: ICG Multiplier Register Read: (ICGMR) Write: See page 97. Reset: ICG Trim Register Read: (ICGTR) Write: See page 98. Reset: ICG Divider Control Read: Register (ICGDVR) Write: See page 98. Reset: ICG DCO Stage Control Read: Register (ICGDSR) Write: See page 98. Reset: Read: $003B Reserved Write: Reset: $003C ADC Status and Control Read: Register (ADSCR) Write: See page 52. Reset: ADC Data Register Read: (ADR) Write: See page 53. Reset: ADC Clock Register Read: (ADCLK) Write: See page 54. Reset: Read: $003F Unimplemented Write: Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0035
Indeterminate after reset CMIE 0 CMF 0 0 N6 0 TRIM7 1 0 TRIM6 0 CMON 0 N5 0 TRIM5 0 CS 0 N4 1 TRIM4 0 ICGON 1 N3 0 TRIM3 0 DDIV3 0 DSTG7 R 0 DSTG6 R 0 DSTG5 R 0 DSTG4 R U DSTG3 R ICGS 0 N2 1 TRIM2 0 DDIV2 U DSTG2 R ECGON 0 N1 0 TRIM1 0 DDIV1 U DSTG1 R ECGS 0 N0 1 TRIM0 0 DDIV0 U DSTG0 R
$0036
$0037
$0038
$0039
$003A
Unaffected by reset R R R R R R R R
Indeterminate after reset COCO R 0 AD7 0 ADIV2 0 AIEN 0 AD6 0 ADIV1 0 ADCO 0 AD5 0 ADIV0 0 ADCH4 1 AD4 0 ADICLK 0 ADCH3 1 AD3 0 0 0 ADCH2 1 AD2 0 0 0 ADCH1 1 AD1 0 0 0 ADCH0 1 AD0 0 0 0
$003D
$003E
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 34 Freescale Semiconductor
Input/Output (I/O) Section Addr. $FE00 Register Name SIM Break Status Register Read: (SBSR) Write: See page 240. Reset: Bit 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 SBSW NOTE 0 Bit 0 R 0
Note: Writing a 0 clears SBSW. SIM Reset Status Register Read: (SRSR) Write: See page 138. POR: Read: $FE02 SIM Upper Byte Address Write: Register (SUBAR) Reset: SIM Break Flag Control Read: Register (SBFCR) Write: See page 240. Reset: Interrupt Status Register 1 Read: (INT1) Write: See page 145. Reset: Interrupt Status Register 2 Read: (INT2) Write: See page 145. Reset: Interrupt Status Register 3 Read: (INT3) Write: See page 145. Reset: Read: $FE07 Reserved Write: Reset: $FE08 FLASH Control Register Read: (FLCR) Write: See page 39. Reset: POR 1 R PIN 0 R COP 0 R ILOP 0 R ILAD 0 R MODRST 0 R LVI 0 R 0 0 R
$FE01
$FE03
BCFE 0 IF6 R 0 IF14 R 0 0 R 0 R 0 0 0 Bit 15 0 Bit 7 0 BRKE 0
R
R
R
R
R
R
R
IF5 R 0 IF13 R 0 0 R 0 R 0 0 0 14 0 6 0 BRKA 0
IF4 R 0 IF12 R 0 0 R 0 R 0 0 0 13 0 5 0 0 0
IF3 R 0 IF11 R 0 0 R 0 R 0 0 0 12 0 4 0 0 0 R = Reserved
IF2 R 0 IF10 R 0 0 R 0 R 0 HVEN 0 11 0 3 0 0 0
IF1 R 0 IF9 R 0 0 R 0 R 0 MASS 0 10 0 2 0 0 0 U = Unaffected
0 R 0 IF8 R 0 IF16 R 0 R 0 ERASE 0 9 0 1 0 0 0
0 R 0 IF7 R 0 IF15 R 0 R 0 PGM 0 Bit 8 0 Bit 0 0 0 0
$FE04
$FE05
$FE06
Break Address Register High Read: $FE09 (BRKH) Write: See page 239. Reset: Break Address Register Low Read: $FE0A (BRKL) Write: See page 239. Reset: $FE0B Break Status and Control Read: Register (BRKSCR) Write: See page 239. Reset:
= Unimplemented
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 35
Memory Addr. $FE0C Register Name Read: LVI Status Register (LVISR) Write: See page 113. Reset: FLASH Block Protect Read: Register (FLBPR)(1) Write: See page 43. Reset: ICG User Trim Read: Register 5V (ICGTR5)(1) Write: See page 44. Reset: ICG User Trim Read: Register 3V (ICGTR3)(1) Write: See page 44. Reset: Bit 7 LVIOUT 0 BPR7 6 0 0 BPR6 5 0 0 BPR5 4 0 0 BPR4 3 0 0 BPR3 2 0 0 BPR2 1 0 0 BPR1 Bit 0 0 0 BPR0
$FF7E
Unaffected by reset TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
$FF80
Unaffected by reset TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
$FF81
Unaffected by reset
$FFFF
COP Control Register Read: (COPCTL) Write: See page 61. Reset: = Unimplemented
Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset R = Reserved U = Unaffected
1. Non-volatile FLASH register
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 36 Freescale Semiconductor
Input/Output (I/O) Section
.
Table 2-1. Vector Addresses
Vector Priority Lowest Vector IF16 IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 -- -- Address $FFDC $FFDD $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF Vector Timebase Vector (High) Timebase Vector (Low) ADC Conversion Complete Vector (High) ADC Conversion Complete Vector (Low) Keyboard Vector (High) Keyboard Vector (Low) SCI Transmit Vector (High) SCI Transmit Vector (Low) SCI Receive Vector (High) SCI Receive Vector (Low) SCI Error Vector (High) SCI Error Vector (Low) SPI Transmit Vector (High) SPI Transmit Vector (Low) SPI Receive Vector (High) SPI Receive Vector (Low) TIM2 Overflow Vector (High) TIM2 Overflow Vector (Low) TIM2 Channel 1 Vector (High) TIM2 Channel 1 Vector (Low) TIM2 Channel 0 Vector (High) TIM2 Channel 0 Vector (Low) TIM1 Overflow Vector (High) TIM1 Overflow Vector (Low) TIM1 Channel 1 Vector (High) TIM1 Channel 1 Vector (Low) TIM1 Channel 0 Vector (High) TIM1 Channel 0 Vector (Low) ICG Vector (High) ICG Vector (Low) IRQ Vector (High) IRQ Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low)
Highest
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 37
Memory
2.5 Random-Access Memory (RAM)
Addresses $0040 through $023F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
2.6 FLASH Memory
This sub-section describes the operation of the embedded FLASH memory. This memory can be read, programmed, and erased from a single external supply. The program, erase, and read operations are enabled through the use of an internal charge pump.
2.6.1 Functional Description
The FLASH memory is an array of 15,872 bytes (7,680 bytes on MC68HC908GT8) with an additional 36 bytes of user vectors, one byte of block protection and two bytes of ICG user trim storage. An erased bit reads as 1 and a programmed bit reads as a 0. Memory in the FLASH array is organized into two rows per page basis. The page size is 64 bytes per page and the row size is 32 bytes per row. Hence the minimum erase page size is 64 bytes and the minimum program row size is 32 bytes. Program and erase operation operations are facilitated through control bits in FLASH control register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are: * $C000-$FDFF; user memory ($E000-$FDFF on MC68HC908GT8) * $FE08; FLASH control register * $FF7E; FLASH block protect register * $FF80; ICG user trim register (ICGTR5) * $FF81; ICG user trim register (ICGTR3) * $FFDC-$FFFF; these locations are reserved for user-defined interrupt and reset vectors
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 38 Freescale Semiconductor
FLASH Memory
2.6.2 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 $FE08 Bit 7 0 6 0 5 0 4 0 3 HVEN 0 2 MASS 0 1 ERASE 0 Bit 0 PGM 0
Figure 2-3. FLASH Control Register (FLCR) HVEN -- High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS -- Mass Erase Control Bit Setting this read/write bit configures the 16 Kbyte FLASH array for mass erase operation. 1 = MASS erase operation selected 0 = MASS erase operation unselected ERASE -- Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM -- Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation unselected
2.6.3 FLASH Page Erase Operation
Use the following procedure to erase a page (64 bytes) of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 36-byte user interrupt vectors area also forms a page. Any FLASH memory page can be erased alone.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 39
Memory
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
Set the ERASE bit and clear the MASS bit in the FLASH control register. Read the FLASH block protect register. Write any data to any FLASH location within the address range of the block to be erased. Wait for a time, tNVS (minimum 10 s). Set the HVEN bit. Wait for a time, tErase (minimum 1 ms or 4 ms). Clear the ERASE bit. Wait for a time, tNVH (minimum 5 s). Clear the HVEN bit. After time, tRCV (typical 1 s), the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. CAUTION A page erase of the vector page will erase the internal oscillator trim values at $FF80 and $FF81.
In applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time.
2.6.4 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read as a 1: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS (minimum 10 s). 5. Set the HVEN bit. 6. Wait for a time, tMErase (minimum 4 ms). 7. Clear the ERASE and MASS bits. NOTE Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). 8. Wait for a time, tNVHL (minimum 100 s). 9. Clear the HVEN bit. 10. After time, tRCV (typical 1 s), the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations
1. When in monitor mode, with security sequence failed (see 19.3.2 Security), write to the FLASH block protect register instead of any FLASH address. MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 40 Freescale Semiconductor
FLASH Memory
must be performed in the order as shown, but other unrelated operations may occur between the steps. CAUTION A mass erase will erase the internal oscillator trim values at $FF80 and $FF81.
2.6.5 FLASH Program/Read Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the following step-by-step procedure to program a row of FLASH memory Figure 2-4 is a flowchart of the programming algorithm. NOTE Only bytes which are currently $FF may be programmed. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range desired. 4. Wait for a time, tNVS (minimum 10 s). 5. Set the HVEN bit. 6. Wait for a time, tPGS (minimum 5 s). 7. Write data to the FLASH address being programmed(1). 8. Wait for time, tPROG (minimum 30 s). 9. Repeat step 7 and 8 until all desired bytes within the row are programmed. 10. Clear the PGM bit(1). 11. Wait for time, tNVH (minimum 5 s). 12. Clear the HVEN bit. 13. After time, tRCV (typical 1 s), the memory can be accessed in read mode again. NOTE The COP register at location $FFFF should not be written between steps 5-12, when the HVEN bit is set. Since this register is located at a valid FLASH address, unpredictable behavior may occur if this location is written while HVEN is set. This program sequence is repeated throughout the memory until all data is programmed. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed tPROG maximum, see 20.20 Memory Characteristics.
1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, tPROG maximum. MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 41
Memory
Algorithm for programming a row (32 bytes) of FLASH memory
1
SET PGM BIT
2
READ THE FLASH BLOCK PROTECT REGISTER
3
WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED
4
WAIT FOR A TIME, tNVS
5
SET HVEN BIT
6
WAIT FOR A TIME, tPGS
7
WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED
8
WAIT FOR A TIME, tPROG
COMPLETED PROGRAMMING THIS ROW? N 10
Y
CLEAR PGM BIT
11
WAIT FOR A TIME, tNVH
Note: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG max. This row program algorithm assumes the row/s to be programmed are initially erased.
12 CLEAR HVEN BIT
13
WAIT FOR A TIME, tRCV
END OF PROGRAMMING
Figure 2-4. FLASH Programming Flowchart
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 42 Freescale Semiconductor
FLASH Memory
2.6.6 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. This protection is done by using of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends at the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. NOTE In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit When the FLBPR is program with all 0's, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1's), the entire memory is accessible for program and erase. When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in 2.6.7 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF or $FE, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also allows entry from reset into the monitor mode.
2.6.7 FLASH Block Protect Register
The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory.
Address: Read: Write: Reset: $FF7E Bit 7 BPR7 6 BPR6 5 BPR5 4 BPR4 3 BPR3 2 BPR2 1 BPR1 Bit 0 BPR0
Unaffected by reset. Initial value from factory is 1. Write to this register is by a programming sequence to the FLASH memory.
Figure 2-5. FLASH Block Protect Register (FLBPR) BPR[7:0] -- FLASH Block Protect Bits These eight bits represent bits [13:6] of a 16-bit memory address. Bit 15 and Bit 14 are 1s and bits [5:0] are 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be $XX00, $XX40, $XX80, and $XXC0 (64 bytes page boundaries) within the FLASH memory.
16-BIT MEMORY ADDRESS START ADDRESS OF FLASH 1 BLOCK PROTECT
1
FLBPR VALUE
0
0
0
0
0
0
Figure 2-6. FLASH Block Protect Start Address
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 43
Memory
Table 2-2. Examples of Protect Address Ranges
BPR[7:0] $00 $01 (0000 0001) $02 (0000 0010) $03 (0000 0011) $04 (0000 0100) $FC (1111 1100) $FD (1111 1101) $FE (1111 1110) $FF Addresses of Protect Range The entire FLASH memory is protected. $C040 (1100 0000 0100 0000) -- $FFFF $C080 (1100 0000 1000 0000) -- $FFFF $C0C0 (1100 0000 1100 0000) -- $FFFF $C100 (1100 0001 0000 0000) -- $FFFF and so on... $FF00 (1111 1111 0000 0000) -- FFFF $FF40 (1111 1111 0100 0000) -- $FFFF FLBPR and vectors are protected $FF80 (1111 1111 1000 0000) -- FFFF Vectors are protected The entire FLASH memory is not protected.
2.6.8 ICG User Trim Registers (ICGTR5 and ICGTR3)
The ICG user trim register are two normal bytes of FLASH memory which are allocated for the user to store copies of the ICG trim register (ICGTR) value. ICGTR5 is allocated for storage of the trim value when a 5-V supply is used, ICGTR3 for storage of the trim value when a 3-V supply is used. Representative trim values are programmed into these locations by Freescale but they may be erased and reprogrammed by the user at any time. Storage and retrieval of data in these registers is not automatic and must be performed programmatically. Typically, these locations are programmed by the user during an in-system calibration procedure and one of them, depending on the application supply voltage, is subsequently used by the user's initialization code to configure the ICG each time following a reset. ICGTR5 is used by the MC68HC908GT16 monitor ROM program during its initialization sequence if monitor mode was entered while clocking from the ICG. If the contents of ICGTR5 are not $FF then the contents are copied to ICGTR. NOTE The contents of ICGTR3 are not utilized by the monitor ROM program.
Address: ICGTR5, $FF80 and ICGTR3, $FF81 Bit 7 Read: Write: Reset: TRIM7 6 TRIM6 5 TRIM5 4 TRIM4 3 TRIM3 2 TRIM2 1 TRIM1 Bit 0 TRIM0
Unaffected by reset. Initial value from factory is 1. Write to this register is by a programming sequence to the FLASH memory.
Figure 2-7. ICG User Trim Registers (ICGTR5 and ICGTR3) TRIM[7:0] -- ICG Trim Factor Bits These bits are copied by the monitor ROM program following a reset, if monitor mode was entered while clocking from the ICG and may be copied by the user's initialization code to the ICG trim register (ICGTR).
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 44 Freescale Semiconductor
FLASH Memory
2.6.9 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode.
2.6.10 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The STOP instruction should not be executed while performing a program or erase operation on the FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode NOTE Standby mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 45
Memory
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 46 Freescale Semiconductor
Chapter 3 Analog-to-Digital Converter (ADC)
3.1 Introduction
This section describes the 8-bit analog-to-digital converter (ADC).
3.2 Features
Features of the ADC module include: * Eight channels with multiplexed input * Linear successive approximation with monotonicity * 8-bit resolution * Single or continuous conversion * Conversion complete flag or conversion complete interrupt * Selectable ADC clock
3.3 Functional Description
The ADC provides eight pins for sampling external sources at pins PTB7/AD7-PTB0/AD0. An analog multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage in (VADIN). VADIN is converted by the successive approximation register-based analog-to-digital converter. When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. See Figure 3-2.
3.3.1 ADC Port I/O Pins
PTB7/AD7-PTB0/AD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC will return a logic 0.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 47
Analog-to-Digital Converter (ADC)
INTERNAL BUS PORTA M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(3) SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA SERIAL PERIPHERAL INTERFACE MODULE PORTB DDRB PTA7/KBD7- PTA0/KBD0(1) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1)(2) PTC3(1)(2) PTC2(1)(2) PTC1(1)(2) PTC0(1)(2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE2 PTE1/RxD PTE0/TxD
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH MC68HC908GT16 -- 15,872 BYTES MC68HC908GT8 -- 7,680 BYTES USER RAM -- 512 BYTES MONITOR ROM -- 304 BYTES FLASH PROGRAMMING ROUTINES ROM -- 720 BYTES USER FLASH VECTOR SPACE -- 36 BYTES
PTE4/OSC1 PTE3/OSC2
INTERNAL CLOCK GENERATOR MODULE
IRQ(3) VREFH VREFL
MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE
PORTE
MONITOR MODULE DDRE
PORTD
DDRD
PORTC
DDRC
SECURITY MODULE
POWER
MONITOR MODE ENTRY MODULE
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
Figure 3-1. Block Diagram Highlighting ADC Block and Pins
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 48 Freescale Semiconductor
Functional Description
INTERNAL DATA BUS READ DDRBx WRITE DDRBx RESET WRITE PTBx DDRBx PTBx PTBx ADC CHANNEL x DISABLE
READ PTBx
DISABLE ADC DATA REGISTER ADC VOLTAGE IN (VADIN) INTERRUPT LOGIC CONVERSION COMPLETE ADC VREFH VREFL ADC CLOCK CGMXCLK BUS CLOCK CLOCK GENERATOR
CHANNEL SELECT
ADCH4-ADCH0
AIEN
COCO
ADIV2-ADIV0
ADICLK
Figure 3-2. ADC Block Diagram
3.3.2 ADC Port I/O Pins
PTB7/AD7-PTB0/AD0 are general-purpose I/O pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC will return a logic 0.
3.3.3 Voltage Conversion
When the input voltage to the ADC equals VREFH, the ADC converts the signal to $FF (full scale). If the input voltage equals VREFL, the ADC converts it to $00. Input voltages between VREFH and VREFL are a straight-line linear conversion. NOTE The ADC input voltage must always be greater than VSSA and less than VDDA. VREFH must always be greater than or equal to VREFL.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 49
Analog-to-Digital Converter (ADC)
NOTE Connect the VDDA pin to the same voltage potential as the VDD pin, and connect the VSSA pin to the same voltage potential as the VSS pin. The VDDA pin should be routed carefully for maximum noise immunity.
3.3.4 Conversion Time
Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency. Conversion time = 16 to 17 ADC cycles ADC frequency
Number of bus cycles = conversion time x bus frequency
3.3.5 Conversion
In continuous conversion mode, the ADC data register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit is set after the first conversion and will stay set until the next read of the ADC data register. In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs between writes to the ADSCR. When a conversion is in process and the ADSCR is written, the current conversion data should be discarded to prevent an incorrect reading.
3.3.6 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
3.5 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power-consumption standby modes.
3.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4-ADCH0 bits in the ADC status and control register before executing the WAIT instruction.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 50 Freescale Semiconductor
I/O Signals
3.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry.
3.6 I/O Signals
The ADC module has eight pins shared with port B, PTB7/AD7-PTB0/AD0.
3.6.1 ADC Analog Power Pin (VDDA)
The ADC analog portion uses VDDA as its power pin. Connect the VDDA pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDA for good results. NOTE For maximum noise immunity, route VDDA carefully and place bypass capacitors as close as possible to the package.
3.6.2 ADC Analog Ground Pin (VSSA)
The ADC analog portion uses VSSA as its ground pin. Connect the VSSA pin to the same voltage potential as VSS. NOTE Route VSSA cleanly to avoid any offset errors.
3.6.3 ADC Voltage Reference High Pin (VREFH)
The ADC analog portion uses VREFH as its upper voltage reference pin. The VREFH pin must be connected to the same voltage potential as VDDA. External filtering is often necessary to ensure a clean VREFH for good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values. NOTE For maximum noise immunity, route VREFH carefully and place bypass capacitors as close as possible to the package. Routing VREFH close and parallel to VREFL may improve common mode noise rejection.
3.6.4 ADC Voltage Reference Low Pin (VREFL)
The ADC analog portion uses VREFL as its lower voltage reference pin. The VREFL pin must be connected to the same voltage potential as VSSA. External filtering is often necessary to ensure a clean VREFL for good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values. NOTE For maximum noise immunity, route VREFL carefully and, if not connected to VSS, place bypass capacitors as close as possible to the package. Routing VREFH close and parallel to VREFL may improve common mode noise rejection.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 51
Analog-to-Digital Converter (ADC)
3.6.5 ADC Voltage In (VADIN)
VADIN is the input voltage signal from one of the eight ADC channels to the ADC module.
3.7 I/O Registers
These I/O registers control and monitor ADC operation: * ADC status and control register (ADSCR) * ADC data register (ADR) * ADC clock register (ADCLK)
3.7.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
Address: Read: Write: Reset: $003C Bit 7 COCO R 0 R 6 AIEN 0 = Reserved 5 ADCO 0 4 ADCH4 1 3 ADCH3 1 2 ADCH2 1 1 ADCH1 1 Bit 0 ADCH0 1
Figure 3-3. ADC Status and Control Register (ADSCR) COCO -- Conversions Complete Bit In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion. COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit. In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It always reads as a 0. 1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) NOTE The write function of the COCO bit is reserved. When writing to the ADSCR register, always have a 0 in the COCO bit position. AIEN -- ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO -- ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 52 Freescale Semiconductor
I/O Registers
ADCH4-ADCH0 -- ADC Channel Select Bits ADCH4-ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only eight channels, AD7-AD0, are available on this MCU. The channels are detailed in Table 3-1. Care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. See Table 3-1. The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for reduced power consumption for the MCU when the ADC is not being used. NOTE Recovery from the disabled state requires one conversion cycle to stabilize. The voltage levels supplied from internal reference nodes, as specified in Table 3-1, are used to verify the operation of the ADC converter both in production test and for user applications. Table 3-1. Mux Channel Select(1)
ADCH4 0 0 0 0 0 0 0 0 0 1 1 1 1 ADCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 ADCH2 0 0 0 0 1 1 1 1 0 1 1 1 1 ADCH1 0 0 1 1 0 0 1 1 0 0 0 1 1 ADCH0 0 1 0 1 0 1 0 1 0 0 1 0 1 Input Select PTB0/AD0 PTB1/AD1 PTB1/AD2 PTB2/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6 PTB7/AD7 Reserved VREFH VREFL ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown or reserved.
3.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes.
Address: Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented $003D Bit 7 AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 AD0
Figure 3-4. ADC Data Register (ADR)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 53
Analog-to-Digital Converter (ADC)
3.7.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address: Read: Write: Reset: $003E Bit 7 ADIV2 0 6 ADIV1 0 5 ADIV0 0 4 ADICLK 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 3-5. ADC Clock Register (ADCLK) ADIV2-ADIV0 -- ADC Clock Prescaler Bits ADIV2-ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz. Table 3-2. ADC Clock Divide Ratio
ADIV2 0 0 0 0 1 ADIV1 0 0 1 1 X
(1)
ADIV0 0 1 0 1 X(1)
ADC Clock Rate ADC input clock / 1 ADC input clock / 2 ADC input clock / 4 ADC input clock / 8 ADC input clock / 16
1. X = Don't care
ADICLK -- ADC Input Clock Select Bit ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. 1 = Internal bus clock 0 = Oscillator output clock (CGMXCLK) The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source is not fast enough, the ADC will generate incorrect conversions. See 20.16 ADC Characteristics. fADIC = fCGMXCLK or bus frequency ADIV[2:0] 1 MHz
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 54 Freescale Semiconductor
Chapter 4 Configuration Register (CONFIG)
4.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: * Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) * COP timeout period (262,128 or 8176 COPCLK cycles) * STOP instruction * Computer operating properly module (COP) * Low-voltage inhibit (LVI) module control and voltage trip point selection * Enable/disable the oscillator (OSC) during stop mode * External clock, external crystal, or ICG clock source
4.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the microcontroller unit (MCU), it is recommended that these registers be written immediately after reset. The configuration registers are located at $001E and $001F and may be read at anytime. NOTE On a FLASH device, the options except LVI5OR3 are one-time writable by the user after each reset. The LVI5OR3 bit is one-time writable by the user only after each POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 4-1 and Figure 4-2.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 55
Configuration Register (CONFIG)
Address: Read: Write: Reset:
$001E Bit 7 0 0 6 0 0 = Unimplemented 5 4 3 2 0 0 1 OSCENINSTOP 0 Bit 0 R 0
EXTXTALEN EXTSLOW EXTCLKEN 0 0 R 0 = Reserved
Figure 4-1. Configuration Register 2 (CONFIG2)
Address: Read: Write: Reset: $001F Bit 7 COPRS 0 6 LVISTOP 0 5 LVIRSTD 0 4 LVIPWRD 0 3 LVI5OR3 See Note 2 SSREC 0 1 STOP 0 Bit 0 COPD 0
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Figure 4-2. Configuration Register 1 (CONFIG1) EXTXTALEN -- External Crystal Enable Bit EXTXTALEN enables the external oscillator circuits to be configured for a crystal configuration where the PTE4/OSC1 and PTE3/OSC2 pins are the connections for an external crystal. Clearing the EXTXTALEN bit (default setting) allows the PTE3/OSC2 pin to function as a general-purpose I/O pin. Refer to Table 4-1 for configuration options for the external source. See Chapter 7 Internal Clock Generator (ICG) Module) for a more detailed description of the external clock operation. EXTXTALEN, when set, also configures the clock monitor to expect an external clock source in the valid range of crystals (30 kHz to 100 kHz or 1 MHz to 8 MHz). When EXTXTALEN is clear, the clock monitor will expect an external clock source in the valid range for externally generated clocks when using the clock monitor (60 Hz to 32 MHz). EXTXTALEN, when set, also configures the external clock stabilization divider in the clock monitor for a 4096-cycle timeout to allow the proper stabilization time for a crystal. When EXTXTALEN is clear, the stabilization divider is configured to 16 cycles since an external clock source does not need a startup time. 1 = Allows PTE3/OSC2 to be an external crystal connection. 0 = PTE3/OSC2 functions as an I/O port pin (default). EXTSLOW -- Slow External Crystal Enable Bit The EXTSLOW bit has two functions. It configures the ICG module for a fast (1 MHz to 8 MHz) or slow (30 kHz to 100 kHz) speed crystal. The option also configures the clock monitor operation in the ICG module to expect an external frequency higher (307.2 kHz to 32 MHz) or lower (60 Hz to 307.2 kHz) than the base frequency of the internal oscillator. See Chapter 7 Internal Clock Generator (ICG) Module). 1 = ICG set for slow external crystal operation 0 = ICG set for fast external crystal operation NOTE This bit does not function without setting the EXTCLKEN bit also.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 56 Freescale Semiconductor
Functional Description
EXTCLKEN -- External Clock Enable Bit EXTCLKEN enables an external clock source or crystal/ceramic resonator to be used as a clock input. Setting this bit enables PTE4/OSC1 pin to be a clock input pin. Clearing this bit (default setting) allows the PTE4/OSC1 and PTE3/OSC2 pins to function as a general-purpose input/output (I/O) pin. Refer to Table 4-1 for configuration options for the external source. See Chapter 7 Internal Clock Generator (ICG) Module) for a more detailed description of the external clock operation. 1 = Allows PTE4/OSC1 to be an external clock connection 0 = PTE4/OSC1 and PTE3/OSC2 function as I/O port pins (default). Table 4-1. External Clock Option Settings
External Clock Configuration Bits EXTCLKEN 0 0 1 EXTXTALEN 0 1 0 PTE4 PTE4 OSC1 Pin Function PTE4/OSC1 PTE3/OSC2 PTE3 PTE3 PTE3 Default setting -- external oscillator disabled External oscillator disabled since EXTCLKEN not set External oscillator configured for an external clock source input (square wave) on OSC1 External oscillator configured for an external crystal configuration on OSC1 and OSC2. System will also operate with square-wave clock source in OSC1. Description
1
1
OSC1
OSC2
OSCENINSTOP -- Oscillator Enable In Stop Mode Bit OSCENINSTOP, when set, will enable the internal clock generator module to continue to generate clocks (either internal, ICLK, or external, ECLK) in stop mode. See Chapter 7 Internal Clock Generator (ICG) Module). This function is used to keep the timebase running while the rest of the microcontroller stops. See Chapter 17 Timebase Module (TBM). When clear, all clock generation will cease and both ICLK and ECLK will be forced low during stop mode. The default state for this option is clear, disabling the ICG in stop mode. 1 = Oscillator enabled to operate during stop mode 0 = Oscillator disabled during stop mode (default) NOTE This bit has the same functionality as the OSCSTOPENB CONFIG bit in MC68HC908GP32 and MC68HC908GR8 parts. COPRS -- COP Rate Select Bit COPD selects the COP timeout period. Reset clears COPRS. See Chapter 5 Computer Operating Properly (COP) Module 1 = COP timeout period = 262,128 COPCLK cycles 0 = COP timeout period = 8176 COPCLK cycles LVISTOP -- LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode LVIRSTD -- LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. See Chapter 10 Low-Voltage Inhibit (LVI). 1 = LVI module resets disabled 0 = LVI module resets enabled
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 57
Configuration Register (CONFIG)
LVIPWRD -- LVI Power Disable Bit LVIPWRD disables the LVI module. See Chapter 10 Low-Voltage Inhibit (LVI). 1 = LVI module power disabled 0 = LVI module power enabled LVI5OR3 -- LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module. See Chapter 10 Low-Voltage Inhibit (LVI) The voltage mode selected for the LVI should match the operating VDD. See Chapter 20 Electrical Specifications for the LVI's voltage trip points for each of the modes. 1 = LVI operates in 5-V mode. 0 = LVI operates in 3-V mode. NOTE The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. 1 = Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLCK cycles NOTE Exiting stop mode by an LVI reset will result in the long stop recovery. The short stop recovery delay can be enabled when using the internal oscillator, a crystal, or a ceramic resonator and the OSCENINSTOP bit is set. The short stop recovery delay can be enabled when an external oscillator is used, regardless of the OSCENINSTOP setting. The short stop recovery delay must be disabled (SSREC = 0) when the OSCENINSTOP bit is cleared. STOP -- STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. See Chapter 5 Computer Operating Properly (COP) Module. 1 = COP module disabled 0 = COP module enabled
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 58 Freescale Semiconductor
Chapter 5 Computer Operating Properly (COP) Module
5.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register.
5.2 Functional Description
Figure 5-1 shows the structure of the COP module.
SIM MODULE BUSCLKX4 12-BIT SIM COUNTER SIM RESET CIRCUIT RESET STATUS REGISTER
CLEAR ALL STAGES
CLEAR STAGES 5-12
INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE
COP CLOCK
COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) CLEAR COP COUNTER
Figure 5-1. COP Block Diagram
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 59
COP TIMEOUT
Computer Operating Properly (COP) Module
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 COPCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 8176 COPCLK cycle overflow option, a 32.768-kHz crystal gives a COP timeout period of 250 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the prescaler. NOTE Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 COPCLK cycles and sets the COP bit in the reset status register (RSR). In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held at VTST. During the break state, VTST on the RST pin disables the COP. NOTE Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
5.3 I/O Signals
The following paragraphs describe the signals shown in Figure 5-1.
5.3.1 COPCLK
COPCLK is a clock generated by the clock selection circuit in the internal clock generator (ICG). See 7.3.5 Clock Selection Circuit for more details.
5.3.2 STOP Instruction
The STOP instruction clears the COP prescaler.
5.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 5.4 COP Control Register) clears the COP counter and clears bits 12 through 5 of the prescaler. Reading the COP control register returns the low byte of the reset vector.
5.3.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
5.3.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 60 Freescale Semiconductor
COP Control Register
5.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler.
5.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Chapter 4 Configuration Register (CONFIG).
5.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See Chapter 4 Configuration Register (CONFIG).
5.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 Low byte of reset vector Clear COP counter Unaffected by reset
Figure 5-2. COP Control Register (COPCTL)
5.5 Interrupts
The COP does not generate central processor unit (CPU) interrupt requests.
5.6 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs.
5.7 Low-Power Modes
The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes.
5.7.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 61
Computer Operating Properly (COP) Module
5.7.2 Stop Mode
Stop mode turns off the COPCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction is disabled, execution of a STOP instruction results in an illegal opcode reset.
5.8 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on the RST pin.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 62 Freescale Semiconductor
Chapter 6 Central Processor Unit (CPU)
6.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
6.2 Features
Features of the CPU include: * Object code fully upward-compatible with M68HC05 Family * 16-bit stack pointer with stack manipulation instructions * 16-bit index register with x-register manipulation instructions * 8-MHz CPU internal bus frequency * 64-Kbyte program/data memory space * 16 addressing modes * Memory-to-memory data moves without using accumulator * Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions * Enhanced binary-coded decimal (BCD) data handling * Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes * Low-power stop and wait modes
6.3 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 63
Central Processor Unit (CPU)
7 15 H 15 15 X 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V11HINZC CONDITION CODE REGISTER (CCR) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 6-2. Accumulator (A)
6.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X X = Indeterminate 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 6-3. Index Register (H:X)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 64 Freescale Semiconductor
CPU Registers
6.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 6-4. Stack Pointer (SP) NOTE The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
6.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0
Figure 6-5. Program Counter (PC)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 65
Central Processor Unit (CPU)
6.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: Write: Reset: V X X = Indeterminate 6 1 1 5 1 1 4 H X 3 I 1 2 N X 1 Z X Bit 0 C X
Figure 6-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 66 Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z -- Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
6.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
6.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.5.1 Wait Mode
The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. * Disables the CPU clock
6.5.2 Stop Mode
The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. * Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
6.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by: * Loading the instruction register with the SWI instruction * Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 67
Central Processor Unit (CPU)
6.7 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set. Table 6-1. Instruction Set Summary (Sheet 1 of 6)
Address Mode Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel
Operation
Description
VH I NZC
Add with Carry
A (A) + (M) + (C)
-
IMM DIR EXT IX2 IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4
ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff
Add without Carry
A (A) + (M)
-
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
- - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
Logical AND
A (A) & (M)
0--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
--
38 dd 48 58 68 ff 78 9E68 ff 37 dd 47 57 67 ff 77 9E67 ff 24 11 13 15 17 19 1B 1D 1F 25 27 90 92 28 29 22 rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr
Arithmetic Shift Right
b7 b0
C
--
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL - - - - - - REL - - - - - - REL
BCLR n, opr
Clear Bit n in M
Mn 0
BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 - - - - - - REL - - - - - - REL - - - - - - REL
3 3
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 68 Freescale Semiconductor
Cycles
2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 3 3 3 3 3
Effect on CCR
Operand
Instruction Set Summary
Table 6-1. Instruction Set Summary (Sheet 2 of 6)
Address Mode Opcode Source Form
BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
VH I NZC
- - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT - IX2 IX1 IX SP1 SP2
24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A
rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr
Bit Test
(A) & (M)
0--
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1 - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
-----
BRN rel
Branch Never
PC (PC) + 2
- - - - - - REL
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
-----
BSET n,opr
Set Bit n in M
Mn 1
DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR IMM - - - - - - IMM IX1+ IX+ SP1 - - - - - 0 INH - - 0 - - - INH
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (X) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI Clear Carry Bit Clear Interrupt Mask
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 69
Cycles
3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2
Effect on CCR
Operand
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 3 of 6)
Address Mode Opcode Source Form
CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA
Operation
Description
M $00 A $00 X $00 H $00 M $00 M $00 M $00
VH I NZC
Clear
DIR INH INH 0 - - 0 1 - INH IX1 IX SP1 IMM DIR EXT IX2 IX1 IX SP1 SP2 DIR INH INH 1 IX1 IX SP1 IMM DIR IMM DIR EXT IX2 IX1 IX SP1 SP2 INH
3F dd 4F 5F 8C 6F ff 7F 9E6F ff A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff
Compare A with M
(A) - (M)
--
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
0--
33 dd 43 53 63 ff 73 9E63 ff 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B dd rr rr rr ff rr rr ff rr ii ii+1 dd ii dd hh ll ee ff ff ff ee ff
Compare H:X with M
--
Compare X with M
(X) - (M)
--
Decimal Adjust A
(A)10
U--
DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP
A (A) - 1 or M (M) - 1 or X (X) - 1 PC (PC) + 3 + rel ? (result) 0 DIR PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 - - - - - - INH PC (PC) + 3 + rel ? (result) 0 IX1 PC (PC) + 2 + rel ? (result) 0 IX PC (PC) + 4 + rel ? (result) 0 SP1 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH INH - IX1 IX SP1 INH IMM DIR EXT - IX2 IX1 IX SP1 SP2 DIR INH - INH IX1 IX SP1
Decrement
--
3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 ii dd hh ll ee ff ff ff ee ff
Divide
----
Exclusive OR M with A
A (A M)
0--
Increment
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
--
3C dd 4C 5C 6C ff 7C 9E6C ff
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 70 Freescale Semiconductor
Cycles
3 1 1 1 3 2 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 5 3 3 5 4 6 4 1 1 4 3 5 7 2 3 4 4 3 2 4 5 4 1 1 4 3 5
Effect on CCR
Operand
Instruction Set Summary
Table 6-1. Instruction Set Summary (Sheet 4 of 6)
Address Mode Opcode Source Form
JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX
Operation
Description
VH I NZC
PC Jump Address
Jump
DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT IX2 - IX1 IX SP1 SP2 - IMM DIR
BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE
dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
0--
Load H:X from M
H:X (M:M + 1)
0--
Load X from M
X (M)
0--
IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 DD DIX+ - IMD IX+D DIR INH INH IX1 IX SP1
Logical Shift Left (Same as ASL)
C b7 b0
0
--
38 dd 48 58 68 ff 78 9E68 ff 34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42 30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 ii dd hh ll ee ff ff ff ee ff dd dd dd ii dd dd
Logical Shift Right
0 b7 b0
C
--0
Move Unsigned multiply
(M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
0--
- 0 - - - 0 INH
Negate (Two's Complement)
--
No Operation Nibble Swap A
- - - - - - INH - - - - - - INH IMM DIR EXT IX2 - IX1 IX SP1 SP2
Inclusive OR A and M
A (A) | (M)
0--
Push A onto Stack Push H onto Stack Push X onto Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1
- - - - - - INH - - - - - - INH - - - - - - INH
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 71
Cycles
2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 4 1 1 4 3 5 1 3 2 3 4 4 3 2 4 5 2 2 2
Effect on CCR
Operand
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 5 of 6)
Address Mode Opcode Source Form
PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP
Operation
Pull A from Stack Pull H from Stack Pull X from Stack
Description
SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
VH I NZC
- - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
86 8A 88 39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff 9C
Rotate Left through Carry
C b7 b0
--
Rotate Right through Carry
b7 b0
C
--
Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
- - - - - - INH
RTI
Return from Interrupt
INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 IX1 IX SP1 SP2
81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff dd hh ll ee ff ff ff ee ff dd ii dd hh ll ee ff ff ff ee ff
Subtract with Carry
A (A) - (M) - (C)
--
Set Carry Bit Set Interrupt Mask
C1 I1
- - - - - 1 INH - - 1 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 - DIR
Store A in M
M (A)
0--
Store H:X in M Enable Interrupts, Stop Processing, Refer to MCU Documentation
(M:M + 1) (H:X) I 0; Stop Processing
0--
- - 0 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
Store X in M
M (X)
0--
Subtract
A (A) - (M)
--
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 72 Freescale Semiconductor
Cycles
2 2 2 4 1 1 4 3 5 4 1 1 4 3 5 1 7 4 2 3 4 4 3 2 4 5 1 2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5
Effect on CCR
Operand
Opcode Map
Table 6-1. Instruction Set Summary (Sheet 6 of 6)
Address Mode Opcode Source Form Operation Description
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
VH I NZC
SWI
Software Interrupt
- - 1 - - - INH
83
TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS WAIT A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH INH - IX1 IX SP1
84 97 85 3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94 8F
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
0--
Transfer SP to H:X Transfer X to A Transfer H:X to SP Enable Interrupts; Wait for Interrupt
H:X (SP) + 1 A (X) (SP) (H:X) - 1 I bit 0; Inhibit CPU clocking until interrupted n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
- - - - - - INH - - - - - - INH - - - - - - INH - - 0 - - - INH
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() -( ) # ? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
6.8 Opcode Map
See Table 6-2.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 73
Cycles
9 2 1 1 3 1 1 3 2 4 2 1 2 1
Effect on CCR
Operand
74
Bit Manipulation DIR DIR
MSB LSB
Central Processor Unit (CPU)
Table 6-2. Opcode Map
Branch REL 2 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL DIR 3 INH 4 Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1 SP1 9E6 IX 7 Control INH INH 8 9 IMM A 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM DIR B EXT C 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT Register/Memory IX2 SP2 D 4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2 9ED 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 IX1 E SP1 9EE 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 IX F 0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
0 1 2
3 4 5 6 7 8 9 A B C D E
F
4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
MSB LSB
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
0
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
0
5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
Chapter 7 Internal Clock Generator (ICG) Module)
7.1 Introduction
The internal clock generator module (ICG) is used to create a stable clock source for the microcontroller without using any external components. The ICG generates the oscillator output clock (CGMXCLK), which is used by the low-voltage inhibit (LVI) and other modules. The ICG also generates the clock generator output (CGMOUT), which is fed to the system integration module (SIM) to create the bus clocks. The bus frequency will be one-fourth the frequency of CGMXCLK and one-half the frequency of CGMOUT. Finally, the ICG generates the timebase clock (TBMCLK), which is used in the timebase module (TBM) and the computer operating properly (COP) clock (COPCLK) which is used by the COP module.
7.2 Features
The ICG has these features: * Selectable external clock generator, either 1-pin external source or 2-pin crystal, multiplexed with port pins * Internal clock generator with programmable frequency output in integer multiples of a nominal frequency (307.2 kHz 25 percent) * Frequency adjust (trim) register to improve variability to 4 percent * Bus clock software selectable from either internal or external clock (bus frequency range from 76.8 kHz 25 percent to 9.75 MHz 25 percent in 76.8-kHz increments NOTE Do not exceed the maximum bus frequency of 8 MHz at 5.0 V and 4 MHz at 3.0 V. * * Timebase clock automatically selected from external if external clock is available Clock monitor for both internal and external clocks
7.3 Functional Description
The ICG, shown in Figure 7-2, contains these major submodules: * Clock enable circuit * Internal clock generator * External clock generator * Clock monitor circuit * Clock selection circuit
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 75
Internal Clock Generator (ICG) Module)
INTERNAL BUS PORTA M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(3) SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA SERIAL PERIPHERAL INTERFACE MODULE PORTB DDRB PTA7/KBD7- PTA0/KBD0(1) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1)(2) PTC3(1)(2) PTC2(1)(2) PTC1(1)(2) PTC0(1)(2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE2 PTE1/RxD PTE0/TxD
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH MC68HC908GT16 -- 15,872 BYTES MC68HC908GT8 -- 7,680 BYTES USER RAM -- 512 BYTES MONITOR ROM -- 304 BYTES FLASH PROGRAMMING ROUTINES ROM -- 720 BYTES USER FLASH VECTOR SPACE -- 36 BYTES
PTE4/OSC1 PTE3/OSC2
INTERNAL CLOCK GENERATOR MODULE
IRQ(3) VREFH VREFL
MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE
PORTE
MONITOR MODULE DDRE
PORTD
DDRD
PORTC
DDRC
SECURITY MODULE
POWER
MONITOR MODE ENTRY MODULE
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
Figure 7-1. Block Diagram Highlighting ICG Module and Pins
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 76 Freescale Semiconductor
Functional Description
CS RESET CLOCK SELECTION CIRCUIT
CGMOUT CGMXCLK TBMCLK COPCLK
IOFF EOFF CMON CLOCK MONITOR CIRCUIT ECGS ICGS
FICGS DDIV[3:0] N[6:0} TRIM[7:0] INTERNAL CLOCK GENERATOR DSTG[7:0] ICLK IBASE ICGEN
SIMOSCEN OSCENINSTOP EXTCLKEN ECGON ICGON ECGEN EXTXTALEN EXTSLOW EXTERNAL CLOCK GENERATOR ECLK CLOCK/PIN ENABLE CIRCUIT
INTERNAL TO MCU EXTERNAL NAME NAME
PTE4 LOGIC OSC1 PTE4 OSC2 PTE3
PTE3 LOGIC
CONFIG2 REGISTER BIT TOP LEVEL SIGNAL
NAME NAME
REGISTER BIT MODULE SIGNAL
Figure 7-2. ICG Module Block Diagram
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 77
Internal Clock Generator (ICG) Module)
7.3.1 Clock Enable Circuit
The clock enable circuit is used to enable the internal clock (ICLK) or external clock (ECLK) and the port logic which is shared with the oscillator pins (OSC1 and OSC2). The clock enable circuit generates an ICG stop (ICGSTOP) signal which stops all clocks (ICLK, ECLK, and the low-frequency base clock, IBASE). ICGSTOP is set and the ICG is disabled in stop mode if the oscillator enable stop bit (OSCENINSTOP) in the CONFIG2 register is clear. The ICG clocks will be enabled in stop mode if OSCENINSTOP is high. The internal clock enable signal (ICGEN) turns on the internal clock generator which generates ICLK. ICGEN is set (active) whenever the ICGON bit is set and the ICGSTOP signal is clear. When ICGEN is clear, ICLK and IBASE are both low. The external clock enable signal (ECGEN) turns on the external clock generator which generates ECLK. ECGEN is set (active) whenever the ECGON bit is set and the ICGSTOP signal is clear. ECGON cannot be set unless the external clock enable (EXTCLKEN) bit in the CONFIG2 register is set. when ECGEN is clear, ECLK is low. The port E4 enable signal (PE4EN) turns on the port E4 logic. Since port E4 is on the same pin as OSC1, this signal is only active (set) when the external clock function is not desired. Therefore, PE4EN is clear when ECGON is set. PE4EN is not gated with ICGSTOP, which means that if the ECGON bit is set, the port E4 logic will remain disabled in stop mode. The port E3 enable signal (PE3EN) turns on the port E3 logic. Since port E3 is on the same pin as OSC2, this signal is only active (set) when 2-pin oscillator function is not desired. Therefore, PE3EN is clear when ECGON and the external crystal enable (EXTXTALEN) bit in the CONFIG2 register are both set. PE3EN is not gated with ICGSTOP, which means that if ECGON and EXTXTALEN are set, the port E3 logic will remain disabled in stop mode.
7.3.2 Internal Clock Generator
The internal clock generator, shown in Figure 7-3, creates a low frequency base clock (IBASE), which operates at a nominal frequency (fNOM) of 307.2 kHz 25 percent, and an internal clock (ICLK) which is an integer multiple of IBASE. This multiple is the ICG multiplier factor (N), which is programmed in the ICG multiplier register (ICGMR). The internal clock generator is turned off and the output clocks (IBASE and ICLK) are held low when the internal clock generator enable signal (ICGEN) is clear. The internal clock generator contains: * A digitally controlled oscillator * A modulo N divider * A frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators * A digital loop filter
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 78 Freescale Semiconductor
Functional Description
ICGEN FICGS DSTG[7:0] + DIGITAL LOOP FILTER - -- TRIM[7:0] N[6:0] DDIV[3:0] DIGITALLY CONTROLLED OSCILLATOR
VOLTAGE AND CURRENT REFERENCES
++
ICLK
FREQUENCY COMPARATOR CLOCK GENERATOR
MODULO N DIVIDER IBASE
NAME NAME
CONFIG2 REGISTER BIT TOP LEVEL SIGNAL
NAME NAME
REGISTER BIT MODULE SIGNAL
Figure 7-3. Internal Clock Generator Block Diagram 7.3.2.1 Digitally Controlled Oscillator The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates the internal clock (ICLK). The clock period of ICLK is dependent on the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]). Because of only a limited number of bits in DDIV and DSTG, the precision of the output (ICLK) is restricted to a precision of approximately 0.202 percent to 0.368 percent when measured over several cycles (of the desired frequency). Additionally, since the propagation delays of the devices used in the DCO ring oscillator are a measurable fraction of the bus clock period, reaching the long-term precision may require alternately running faster and slower than desired, making the worst case cycle-to-cycle frequency variation 6.45 percent to 11.8 percent (of the desired frequency). The valid values of DDIV:DSTG range from $000 to $9FF. For more information on the quantization error in the DCO, see 7.4.4 Quantization Error in DCO Output. 7.3.2.2 Modulo N Divider The modulo N divider creates the low-frequency base clock (IBASE) by dividing the internal clock (ICLK) by the ICG multiplier factor (N), contained in the ICG multiplier register (ICGMR). When N is programmed to a $01 or $00, the divider is disabled and ICLK is passed through to IBASE undivided. When the internal clock generator is stable, the frequency of IBASE will be equal to the nominal frequency (fNOM) of 307.2 kHz 25 percent.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 79
Internal Clock Generator (ICG) Module)
7.3.2.3 Frequency Comparator The frequency comparator effectively compares the low-frequency base clock (IBASE) to a nominal frequency, fNOM. First, the frequency comparator converts IBASE to a voltage by charging a known capacitor with a current reference for a period dependent on IBASE. This voltage is compared to a voltage reference with comparators, whose outputs are fed to the digital loop filter. The dependence of these outputs on the capacitor size, current reference, and voltage reference causes up to 25 percent error in fNOM. 7.3.2.4 Digital Loop Filter The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust the internal clock (ICLK) clock period. The DLF generates the DCO divider control bits (DDIV[3:0]) and the DCO stage control bits (DSTG[7:0]), which are fed to the DCO. The DLF first concatenates the DDIV and DSTG registers (DDIV[3:0]:DSTG[7:0]) and then adds or subtracts a value dependent on the relative error in the low-frequency base clock's period, as shown in Table 7-1. In some extreme error conditions, such as operating at a VDD level which is out of specification, the DLF may attempt to use a value above the maximum ($9FF) or below the minimum ($000). In both cases, the value for DDIV will be between $A and $F. In this range, the DDIV value will be interpreted the same as $9 (the slowest condition). Recovering from this condition requires subtracting (increasing frequency) in the normal fashion until the value is again below $9FF. (If the desired value is $9xx, the value may settle at $Axx through $Fxx. This is an acceptable operating condition.) If the error is less than 5 percent, the internal clock generator's filter stable indicator (FICGS) is set, indicating relative frequency accuracy to the clock monitor. Table 7-1. Correction Sizes from DLF to DCO
Frequency Error of IBASE Compared to fNOM IBASE < 0.85 fNOM 0.85 fNOM < IBASE IBASE < 0.95 fNOM 0.95 fNOM < IBASE IBASE < fNOM fNOM < IBASE IBASE < 1.05 fNOM 1.05 fNOM < IBASE IBASE < 1.15 fNOM 1.15 fNOM < IBASE DDVI[3:0]:DSTG[7:0] Correction -32 (-$020) Maximum Minimum -8 (-$008) Maximum Minimum -1 (-$001) Maximum Minimum +1 (+$001) Maximum Minimum +8 (+$008) Maximum Minimum +32 (+$020) Maximum $x00 to $x20 +2/17 +11.8% $x00 to $x08 $xDF to $xFF +0.5/17 +2/29 +2.94% +6.90% $x00 to $x01 $xF7 to $xFF +0.0625/17 +0.5/30.5 +0.368% +1.64% $x01 to $x00 $xFE to $xFF -0.0625/17.0625 +0.0625/30.9375 -0.366% +0.202% $x08 to $x00 $xFF to $xFE -0.5/17.5 -0.0625/31 -2.86% -0.202% $x20 to $x00 $xFF to $xF7 -2/19 -0.5/31 -10.5% -1.61% Current to New DDIV[3:0]:DSTG[7:0](1) Minimum $xFF to $xDF Relative Correction in DCO -2/31 -6.45%
1. x = Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0] carries or borrows.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 80 Freescale Semiconductor
Functional Description
7.3.3 External Clock Generator
The ICG also provides for an external oscillator or external clock source, if desired. The external clock generator, shown in Figure 7-4, contains an external oscillator amplifier and an external clock input path.
ECGEN INPUT PATH EXTXTALEN EXTERNAL CLOCK GENERATOR EXTSLOW OSC1 PTE4 RB OSC2 PTE3 AMPLIFIER
ECLK
INTERNAL TO MCU EXTERNAL
NAME NAME NAME NAME
CONFIG2 BIT TOP LEVEL SIGNAL REGISTER BIT MODULE SIGNAL C1 X1
R S*
*RS can be 0 (shorted) when used with higherfrequency crystals. Refer to manufacturer's data.
C2
These components are required for external crystal use only.
Figure 7-4. External Clock Generator Block Diagram 7.3.3.1 External Oscillator Amplifier The external oscillator amplifier provides the gain required by an external crystal connected in a Pierce oscillator configuration. The amount of this gain is controlled by the slow external (EXTSLOW) bit in the CONFIG2 register. When EXTSLOW is set, the amplifier gain is reduced for operating low-frequency crystals (32 kHz to 100 kHz). When EXTSLOW is clear, the amplifier gain will be sufficient for 1-MHz to 8-MHz crystals. EXTSLOW must be configured correctly for the given crystal or the circuit may not operate. The amplifier is enabled when the external clock generator enable (ECGEN) signal is set and when the external crystal enable (EXTXTALEN) bit in the CONFIG2 register is set. ECGEN is controlled by the clock enable circuit (see 7.3.1 Clock Enable Circuit) and indicates that the external clock function is desired. When enabled, the amplifier will be connected between the PTE4/OSC1 and PTE3/OSC2 pins. Otherwise, the PTE3/OSC2 pin reverts to its port function.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 81
Internal Clock Generator (ICG) Module)
In its typical configuration, the external oscillator requires five external components: 1. Crystal, X1 2. Fixed capacitor, C1 3. Tuning capacitor, C2 (can also be a fixed capacitor) 4. Feedback resistor, RB 5. Series resistor, RS (Included in Figure 7-4 to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer's data for more information.) 7.3.3.2 External Clock Input Path The external clock input path is the means by which the microcontroller uses an external clock source. The input to the path is the PTE4/OSC1 pin and the output is the external clock (ECLK). The path, which contains input buffering, is enabled when the external clock generator enable signal (ECGEN) is set. When not enabled, the PTE4/OSC1 pin reverts to its port function.
7.3.4 Clock Monitor Circuit
The ICG contains a clock monitor circuit which, when enabled, will continuously monitor both the external clock (ECLK) and the internal clock (ICLK) to determine if either clock source has been corrupted. The clock monitor circuit, shown in Figure 7-5, contains these blocks: * Clock monitor reference generator * Internal clock activity detector * External clock activity detector 7.3.4.1 Clock Monitor Reference Generator The clock monitor uses a reference based on one clock source to monitor the other clock source. The clock monitor reference generator generates the external reference clock (EREF) based on the external clock (ECLK) and the internal reference clock (IREF) based on the internal clock (ICLK). To simplify the circuit, the low-frequency base clock (IBASE) is used in place of ICLK because it always operates at or near 307.2 kHz. For proper operation, EREF must be at least twice as slow as IBASE and IREF must be at least twice as slow as ECLK. To guarantee that IREF is slower than ECLK and EREF is slower than IBASE, one of the signals is divided down. Which signal is divided and by how much is determined by the external slow (EXTSLOW) and external crystal enable (EXTXTALEN) bits in the CONFIG2 register, according to the rules in Table 7-2. NOTE Each signal (IBASE and ECLK) is always divided by four. A longer divider is used on either IBASE or ECLK based on the EXTSLOW bit.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 82 Freescale Semiconductor
Functional Description
CMON FICGS IBASE ICGEN
CMON FICGS IBASE ICGEN EREF ICLK ACTIVITY DETECTOR
IOFF
IOFF
ICGS
ICGS
IBASE ICGON EXTXTALEN EXTSLOW EXTXTALEN EXTSLOW ECGS ECLK ECGEN
EREF
REFERENCE GENERATOR
ESTBCLK IREF
ESTBCLK IREF ECGEN ECLK ECGEN ECLK CMON ECLK ACTIVITY DETECTOR
ECGS
ECGS
EOFF
EOFF
NAME NAME
CONFIG2 REGISTER BIT TOP LEVEL SIGNAL
NAME NAME
REGISTER BIT MODULE SIGNAL
Figure 7-5. Clock Monitor Block Diagram
To conserve size, the long divider (divide by 4096) is also used as an external crystal stabilization divider. The divider is reset when the external clock generator is turned off or in stop mode (ECGEN is clear). When the external clock generator is first turned on, the external clock generator stable bit (ECGS) will be clear. This condition automatically selects ECLK as the input to the long divider. The external stabilization clock (ESTBCLK) will be ECLK divided by 16 when EXTXTALEN is low or 4096 when EXTXTALEN is high. This timeout allows the crystal to stabilize. The falling edge of ESTBCLK is used to set ECGS, which will set after a full 16 or 4096 cycles. When ECGS is set, the divider returns to its normal function. ESTBCLK may be generated by either IBASE or ECLK, but any clocking will only reinforce the set condition. If ECGS is cleared because the clock monitor determined that ECLK was inactive, the divider will revert to a stabilization divider. Since this will change the EREF and IREF divide ratios, it is important to turn the clock monitor off (CMON = 0) after inactivity is detected to ensure valid recovery.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 83
Internal Clock Generator (ICG) Module)
7.3.4.2 Internal Clock Activity Detector The internal clock activity detector, shown in Figure 7-6, looks for at least one falling edge on the low-frequency base clock (IBASE) every time the external reference (EREF) is low. Since EREF is less than half the frequency of IBASE, this should occur every time. If it does not occur two consecutive times, the internal clock inactivity indicator (IOFF) is set. IOFF will be cleared the next time there is a falling edge of IBASE while EREF is low.
CMON EREF CK 1/4 R R D DFFRS IBASE CK S DLF MEASURE OUTPUT CLOCK ICGEN FICGS Q D CK R R Q D CK R DFFRR R Q ICGS DFFRR Q IOFF
NAME NAME
CONFIG2 REGISTER BIT TOP LEVEL SIGNAL
NAME NAME
REGISTER BIT MODULE SIGNAL
Figure 7-6. Internal Clock Activity Detector The internal clock stable bit (ICGS) is also generated in the internal clock activity detector. ICGS is set when the internal clock generator's filter stable signal (FICGS) indicates that IBASE is within about 5 percent of the target 307.2 kHz 25 percent for two consecutive measurements. ICGS is cleared when FICGS is clear, the internal clock generator is turned off or is in stop mode (ICGEN is clear), or when IOFF is set. 7.3.4.3 External Clock Activity Detector The external clock activity detector, shown in Figure 7-7, looks for at least one falling edge on the external clock (ECLK) every time the internal reference (IREF) is low. Since IREF is less than half the frequency of ECLK, this should occur every time. If it does not occur two consecutive times, the external clock inactivity indicator (EOFF) is set. EOFF will be cleared the next time there is a falling edge of ECLK while IREF is low. The external clock stable bit (ECGS) is also generated in the external clock activity detector. ECGS is set on a falling edge of the external stabilization clock (ESTBCLK). This will be 4096 ECLK cycles after the external clock generator on bit is set, or the MCU exits stop mode (ECGEN = 1) if the external crystal enable (EXTXTALEN) in the CONFIG2 register is set, or 16 cycles when EXTXTALEN is clear. ECGS is cleared when the external clock generator is turned off or in stop mode (ECGEN is clear) or when EOFF is set.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 84 Freescale Semiconductor
Functional Description
CMON IREF CK 1/4 R R D DFFRS ECLK CK S ESTBCLK ECGEN NAME NAME CONFIG2 REGISTER BIT TOP LEVEL SIGNAL NAME NAME REGISTER BIT MODULE SIGNAL Q D DFFRR CK R Q EGGS R Q EOFF
Figure 7-7. External Clock Activity Detector
7.3.5 Clock Selection Circuit
The clock selection circuit, shown in Figure 7-8, contains two clock switches which generate the oscillator output clock (CGMXCLK) and the timebase clock (TBMCLK) from either the internal clock (ICLK) or the external clock (ECLK). The COP clock (COPCLK) is identical to TBMCLK. The clock selection circuit also contains a divide-by-two circuit which creates the clock generator output clock (CGMOUT), which generates the bus clocks.
CS ICLK ECLK IOFF EOFF RESET VSS ECGON SELECT ICLK ECLK IOFF EOFF FORCE_I FORCE_E OUTPUT TBMCLK COPCLK SYNCHRONIZING CLOCK SWITCHER SYNCHRONIZING CLOCK SWITCHER DIV2 OUTPUT CGMXCLK
CGMOUT
SELECT ICLK ECLK IOFF EOFF FORCE_I FORCE_E
NAME NAME
CONFIG2 REGISTER BIT TOP LEVEL SIGNAL
NAME NAME
REGISTER BIT MODULE SIGNAL
Figure 7-8. Clock Selection Circuit Block Diagram
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 85
Internal Clock Generator (ICG) Module)
7.3.5.1 Clock Selection Switches The first switch creates the oscillator output clock (CGMXCLK) from either the internal clock (ICLK) or the external clock (ECLK), based on the clock select bit (CS; set selects ECLK, clear selects ICLK). When switching the CS bit, both ICLK and ECLK must be on (ICGON and ECGON set). The clock being switched to also must be stable (ICGS or ECGS set). The second switch creates the timebase clock (TBMCLK) and the COP clock (COPCLK) from ICLK or ECLK based on the external clock on bit. When ECGON is set, the switch automatically selects the external clock, regardless of the state of the ECGS bit. 7.3.5.2 Clock Switching Circuit To robustly switch between the internal clock (ICLK) and the external clock (ECLK), the switch assumes the clocks are completely asynchronous, so a synchronizing circuit is required to make the transition. When the select input (the clock select bit for the oscillator output clock switch or the external clock on bit for the timebase clock switch) is changed, the switch will continue to operate off the original clock for between one and two cycles as the select input is transitioned through one side of the synchronizer. Next, the output will be held low for between one and two cycles of the new clock as the select input transitions through the other side. Then the output starts switching at the new clock's frequency. This transition guarantees that no glitches will be seen on the output even though the select input may change asynchronously to the clocks. The unpredictably of the transition period is a necessary result of the asynchronicity. The switch automatically selects ICLK during reset. When the clock monitor is on (CMON is set) and it determines one of the clock sources is inactive (as indicated by the IOFF or EOFF signals), the circuit is forced to select the active clock. There are no clocks for the inactive side of the synchronizer to properly operate, so that side is forced deselected. However, the active side will not be selected until one to two clock cycles after the IOFF or EOFF signal transitions.
7.4 Usage Notes
The ICG has several features which can provide protection to the microcontroller if properly used. Other features can greatly simplify usage of the ICG if certain techniques are employed. This section describes several possible ways to use the ICG and its features. These techniques are not the only ways to use the ICG and may not be optimum for all environments. In any case, these techniques should be used only as a template, and the user should modify them according to the application's requirements. These notes include: * Switching clock sources * Enabling the clock monitor * Using clock monitor interrupts * Quantization error in digitally controlled oscillator (DCO) output * Switching internal clock frequencies * Nominal frequency settling time * Improving frequency settling time * Trimming frequency
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 86 Freescale Semiconductor
Usage Notes
7.4.1 Switching Clock Sources
* * * * * Switching from one clock source to another requires both clock sources to be enabled and stable. A simple flow requires: Enable desired clock source Wait for it to become stable Switch clocks Disable previous clock source
The key point to remember in this flow is that the clock source cannot be switched (CS cannot be written) unless the desired clock is on and stable. A short assembly code example of how to employ this flow is shown in Figure 7-9.
;* Clock Switching Code Example ;* This code switches from internal to external clock ;* Clock monitor and interrupts are not enabled ;* ICG Clock Switch SwitchItoE: bset ECGON,ICGCR brclr ECGS,ICGCR,* bset CS,ICGCR bclr ICGON,ICGCR
; ; ; ;
turn on external oscillator wait until external clock engaged select external clock for bus turn off internal clock (if desired)
Figure 7-9. Code Example for Switching Clock Sources
7.4.2 Enabling the Clock Monitor
Many applications require the clock monitor to determine if one of the clock sources has become inactive, so the other can be used to recover from a potentially dangerous situation. Using the clock monitor requires both clocks to be active (ECGON and ICGON both set). To enable the clock monitor, both clocks also must be stable (ECGS and ICGS both set). This is to prevent the use of the clock monitor when a clock is first turned on and potentially unstable. Enabling the clock monitor and clock monitor interrupts requires a flow similar to this: * Enable the alternate clock source * Wait for both clock sources to be stable * Switch to the desired clock source if necessary * Enable the clock monitor * Enable clock monitor interrupts These events must happen in sequence. A short assembly code example of how to employ this flow is shown in Figure 7-10.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 87
Internal Clock Generator (ICG) Module)
;* Clock Monitor Enable Code Example ;* This code turns on both clocks, selects the desired one, ;* then turns on the Clock Monitor and CM Interrupt ;* ICG Clock Monitor Enable CMEnable: bset ECGON,ICGCR brclr bset bset bset ECGS,ICGCR,* CS,ICGCR CMON,ICGCR CMIE,ICGCR
; ; ; ; ; ;
turn on external oscillator (assumes internal osc is on) wait until external clock engaged select external clock for bus enable Clock Monitor enable CM interrupt
Figure 7-10. Code Example for Enabling the Clock Monitor
7.4.3 Using Clock Monitor Interrupts
The clock monitor circuit can be used to recover from perilous situations such as crystal loss. To use the clock monitor effectively, these points should be observed: * Enable the clock monitor and clock monitor interrupts. * The first statement in the clock monitor interrupt service routine (CMISR) should be a read to the ICG control register (ICGCR) to verify that the clock monitor flag (CMF) is set. This is also the first step in clearing the CMF bit. * The second statement in the CMISR should be a write to the ICGCR to clear the CMF bit (write the bit low). Writing the bit high will not affect it. This statement does not need to immediately follow the first, but must be contained in the CMISR. * The third statement in the CMISR should be to clear the CMON bit. This is required to ensure proper reconfiguration of the reference dividers. This statement also must be contained in the CMISR. * Although the clock monitor can be enabled only when both clocks are stable (ICGS is set or ECGS is set), it will remain set if one of the clocks goes unstable. * The clock monitor only works if the external slow (EXTSLOW) bit in the CONFIG2 register is set to the correct value. * The internal and external clocks must both be enabled and running to use the clock monitor. * When the clock monitor detects inactivity, the inactive clock is automatically deselected and the active clock selected as the source for CGMXCLK and TBMCLK. The CMISR can use the state of the CS bit to check which clock is inactive. * When the clock monitor detects inactivity, the application may have been subjected to extreme conditions which may have affected other circuits. The CMISR should take any appropriate precautions.
7.4.4 Quantization Error in DCO Output
The digitally controlled oscillator (DCO) is comprised of three major sub-blocks: 1. Binary weighted divider 2. Variable-delay ring oscillator 3. Ring oscillator fine-adjust circuit Each of these blocks affects the clock period of the internal clock (ICLK). Since these blocks are controlled by the digital loop filter (DLF) outputs DDIV and DSTG, the output of the DCO can change only in
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 88 Freescale Semiconductor
Usage Notes
quantized steps as the DLF increments or decrements its output. The following sections describe how each block will affect the output frequency. 7.4.4.1 Digitally Controlled Oscillator The digitally controlled oscillator (DCO) is an inaccurate oscillator which generates the internal clock (ICLK), whose clock period is dependent on the digital loop filter outputs (DSTG[7:0] and DDIV[3:0]). Because of the digital nature of the DCO, the clock period of ICLK will change in quantized steps. This will create a clock period difference or quantization error (Q-ERR) from one cycle to the next. Over several cycles or for longer periods, this error is divided out until it reaches a minimum error of 0.202 percent to 0.368 percent. The dependence of this error on the DDIV[3:0] value and the number of cycles the error is measured over is shown in Table 7-2. Table 7-2. Quantization Error in ICLK
DDIV[3:0] %0000 (min) %0000 (min) %0000 (min) %0001 %0001 %0001 %0010 %0010 %0010 %0011 %0011 %0100 %0100 %0101-%1001 (max) ICLK Cycles 1 4 32 1 4 16 1 4 8 1 4 1 2 1 Bus Cycles NA 1 8 NA 1 4 NA 1 2 NA 1 NA 1 1 ICLK Q-ERR 6.45%-11.8% 1.61%-2.94% 0.202%-0.368% 3.23%-5.88% 0.806%-1.47% 0.202%-0.368% 1.61%-2.94% 0.403%-0.735% 0.202%-0.368% 0.806%-1.47% 0.202%-0.368% 0.403%-0.735% 0.202%-0.368% 0.202%-0.368%
7.4.4.2 Binary Weighted Divider The binary weighted divider divides the output of the ring oscillator by a power of two, specified by the DCO divider control bits (DDIV[3:0]). DDIV maximizes at %1001 (values of %1010 through %1111 are interpreted as %1001), which corresponds to a divide by 512. When DDIV is %0000, the ring oscillator's output is divided by 1. Incrementing DDIV by one will double the period; decrementing DDIV will halve the period. The DLF cannot directly increment or decrement DDIV; DDIV is only incremented or decremented when an addition or subtraction to DSTG carries or borrows. 7.4.4.3 Variable-Delay Ring Oscillator The variable-delay ring oscillator's period is adjustable from 17 to 31 stage delays, in increments of two, based on the upper three DCO stage control bits (DSTG[7:5]). A DSTG[7:5] of %000 corresponds to 17 stage delays; DSTG[7:5] of %111 corresponds to 31 stage delays. Adjusting the DSTG[5] bit has a 6.45 percent to 11.8 percent effect on the output frequency. This also corresponds to the size correction made when the frequency error is greater than 15 percent. The value of the binary weighted divider does not affect the relative change in output clock period for a given change in DSTG[7:5].
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 89
Internal Clock Generator (ICG) Module)
7.4.4.4 Ring Oscillator Fine-Adjust Circuit The ring oscillator fine-adjust circuit causes the ring oscillator to effectively operate at non-integer numbers of stage delays by operating at two different points for a variable number of cycles specified by the lower five DCO stage control bits (DSTG[4:0]). For example: * When DSTG[7:5] is %011, the ring oscillator nominally operates at 23 stage delays. * When DSTG[4:0] is %00000, the ring will always operate at 23 stage delays. * When DSTG[4:0] is %00001, the ring will operate at 25 stage delays for one of 32 cycles and at 23 stage delays for 31 of 32 cycles. * Likewise, when DSTG[4:0] is %11111, the ring operates at 25 stage delays for 31 of 32 cycles and at 23 stage delays for one of 32 cycles. * When DSTG[7:5] is %111, similar results are achieved by including a variable divide-by-two, so the ring operates at 31 stages for some cycles and at 17 stage delays, with a divide-by-two for an effective 34 stage delays, for the remainder of the cycles. Adjusting the DSTG[0] bit has a 0.202 percent to 0.368 percent effect on the output clock period. This corresponds to the minimum size correction made by the DLF, and the inherent, long-term quantization error in the output frequency.
7.4.5 Switching Internal Clock Frequencies
The frequency of the internal clock (ICLK) may need to be changed for some applications. For example, if the reset condition does not provide the correct frequency, or if the clock is slowed down for a low-power mode (or sped up after a low-power mode), the frequency must be changed by programming the internal clock multiplier factor (N). The frequency of ICLK is N times the frequency of IBASE, which is 307.2 kHz 25 percent. Before switching frequencies by changing the N value, the clock monitor must be disabled. This is because when N is changed, the frequency of the low-frequency base clock (IBASE) will change proportionally until the digital loop filter has corrected the error. Since the clock monitor uses IBASE, it could erroneously detect an inactive clock. The clock monitor cannot be re-enabled until the internal clock is stable again (ICGS is set). The following flow is an example of how to change the clock frequency: * Verify there is no clock monitor interrupt by reading the CMF bit. * Turn off the clock monitor. * If desired, switch to the external clock (see 7.4.1 Switching Clock Sources). * Change the value of N. * Switch back to internal (see 7.4.1 Switching Clock Sources), if desired. * Turn on the clock monitor (see 7.4.2 Enabling the Clock Monitor), if desired.
7.4.6 Nominal Frequency Settling Time
Because the clock period of the internal clock (ICLK) is dependent on the digital loop filter outputs (DDIV and DSTG) which cannot change instantaneously, ICLK temporarily will operate at an incorrect clock period when any operating condition changes. This happens whenever the part is reset, the ICG multiply factor (N) is changed, the ICG trim factor (TRIM) is changed, or the internal clock is enabled after inactivity (stop mode or disabled operation). The time that the ICLK takes to adjust to the correct period is known as the settling time.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 90 Freescale Semiconductor
Usage Notes
Settling time depends primarily on how many corrections it takes to change the clock period and the period of each correction. Since the corrections require four periods of the low-frequency base clock (4*IBASE), and since ICLK is N (the ICG multiply factor for the desired frequency) times faster than IBASE, each correction takes 4*N*ICLK. The period of ICLK, however, will vary as the corrections occur. 7.4.6.1 Settling to Within 15 Percent When the error is greater than 15 percent, the filter takes eight corrections to double or halve the clock period. Due to how the DCO increases or decreases the clock period, the total period of these eight corrections is approximately 11 times the period of the fastest correction. (If the corrections were perfectly linear, the total period would be 11.5 times the minimum period; however, the ring must be slightly nonlinear.) Therefore, the total time it takes to double or halve the clock period is 44*N*ICLKFAST. If the clock period needs more than doubled or halved, the same relationship applies, only for each time the clock period needs doubled, the total number of cycles doubles. That is, when transitioning from fast to slow, going from the initial speed to half speed takes 44*N*ICLKFAST; from half speed to quarter speed takes 88*N*ICLKFAST; going from quarter speed to eighth speed takes 176*N*ICLKFAST; and so on. This series can be expressed as (2x-1)*44*N*ICLKFAST, where x is the number of times the speed needs doubled or halved. Since 2x happens to be equal to ICLKSLOW/ICLKFAST, the equation reduces to 44*N*(ICLKSLOW-ICLKFAST). Note that increasing speed takes much longer than decreasing speed since N is higher. This can be expressed in terms of the initial clock period (1) minus the final clock period (2) as such: 15 = abs [ 44N ( 1 - 2 ) ] 7.4.6.2 Settling to Within 5 Percent Once the clock period is within 15 percent of the desired clock period, the filter starts making smaller adjustments. When between 15 percent and 5 percent error, each correction will adjust the clock period between 1.61 percent and 2.94 percent. In this mode, a maximum of eight corrections will be required to get to less than 5 percent error. Since the clock period is relatively close to desired, each correction takes approximately the same period of time, or 4*IBASE. At this point, the internal clock stable bit (ICGS) will be set and the clock frequency is usable, although the error will be as high as 5 percent. The total time to this point is: 5 = abs [ 44N ( 1 - 2 ) ] + 32 IBASE 7.4.6.3 Total Settling Time Once the clock period is within 5 percent of the desired clock period, the filter starts making minimum adjustments. In this mode, each correction will adjust the frequency between 0.202 percent and 0.368 percent. A maximum of 24 corrections will be required to get to the minimum error. Each correction takes approximately the same period of time, or 4*IBASE. Added to the corrections for 15 percent to 5 percent, this makes 32 corrections (128*IBASE) to get from 15 percent to the minimum error. The total time to the minimum error is: tot = abs [ 44N ( 1 - 2 ) ] + 128 IBASE The equations for 15, 5, and tot are dependent on the actual initial and final clock periods 1 and 2, not the nominal. This means the variability in the ICLK frequency due to process, temperature, and voltage must be considered. Additionally, other process factors and noise can affect the actual tolerances of the points at which the filter changes modes. This means a worst case adjustment of up to 35 percent (ICLK
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 91
Internal Clock Generator (ICG) Module)
clock period tolerance plus 10 percent) must be added. This adjustment can be reduced with trimming. Table 7-3 shows some typical values for settling time. Table 7-3. Typical Settling Time Examples
1 1/ (6.45 MHz) 1/ (25.8 MHz) 1/ (25.8 MHz) 1/ (307.2 kHz) 2 1/ (25.8 MHz) 1/ (6.45 MHz) 1/ (307.2 kHz) 1/ (25.8 MHz) N 84 21 1 84 15 430 s 107 s 141 s 11.9 ms 5 535 s 212 s 246 s 12.0 ms tot 850 s 525 s 560 s 12.3 ms
7.4.7 Trimming Frequency on the Internal Clock Generator
The unadjusted frequency of the low-frequency base clock (IBASE), when the comparators in the frequency comparator indicate zero error, will vary as much as 25 percent due to process, temperature, and voltage dependencies. These dependencies are in the voltage and current references, the offset of the comparators, and the internal capacitor. The method of changing the unadjusted operating point is by changing the size of the capacitor. This capacitor is designed with 639 equally sized units. Of that number, 384 of these units are always connected. The remaining 255 units are put in by adjusting the ICG trim factor (TRIM). The default value for TRIM is $80, or 128 units, making the default capacitor size 512. Each unit added or removed will adjust the output frequency by about 0.195 percent of the unadjusted frequency (adding to TRIM will decrease frequency). Therefore, the frequency of IBASE can be changed to 25 percent of its unadjusted value, which is enough to cancel the process variability mentioned before. The best way to trim the internal clock is to use the timer to measure the width of an input pulse on an input capture pin (this pulse must be supplied by the application and should be as long or wide as possible). Considering the prescale value of the timer and the theoretical (zero error) frequency of the bus (307.2 kHz *N/4), the error can be calculated. This error, expressed as a percentage, can be divided by 0.195 percent and the resultant factor added or subtracted from TRIM. This process should be repeated to eliminate any residual error.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
7.5.1 Wait Mode
The ICG remains active in wait mode. If enabled, the ICG interrupt to the CPU can bring the MCU out of wait mode. In some applications, low power-consumption is desired in wait mode and a high-frequency clock is not needed. In these applications, reduce power consumption by either selecting a low-frequency external clock and turn the internal clock generator off or reduce the bus frequency by minimizing the ICG multiplier factor (N) before executing the WAIT instruction.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 92 Freescale Semiconductor
CONFIG2 Options
7.5.2 Stop Mode
The value of the oscillator enable in stop (OSCENINSTOP) bit in the CONFIG2 register determines the behavior of the ICG in stop mode. If OSCENINSTOP is low, the ICG is disabled in stop and, upon execution of the STOP instruction, all ICG activity will cease and the output clocks (CGMXCLK, CGMOUT, COPCLK, and TBMCLK) will be held low. Power consumption will be minimal. If OSCENINSTOP is high, the ICG is enabled in stop and activity will continue. This is useful if the timebase module (TBM) is required to bring the MCU out of stop mode. ICG interrupts will not bring the MCU out of stop mode in this case. During stop mode, if OSCENINSTOP is low, several functions in the ICG are affected. The stable bits (ECGS and ICGS) are cleared, which will enable the external clock stabilization divider upon recovery. The clock monitor is disabled (CMON = 0) which will also clear the clock monitor interrupt enable (CMIE) and clock monitor flag (CMF) bits. The CS, ICGON, ECGON, N, TRIM, DDIV, and DSTG bits are unaffected.
7.6 CONFIG2 Options
Four CONFIG2 register options affect the functionality of the ICG. These options are: 1. EXTCLKEN, external clock enable 2. EXTXTALEN, external crystal enable 3. EXTSLOW, slow external clock 4. OSCENINSTOP, oscillator enable in stop All CONFIG2 options will have a default setting. Refer to Chapter 4 Configuration Register (CONFIG) on how the CONFIG2 register is used.
7.6.1 External Clock Enable (EXTCLKEN)
External clock enable (EXTCLKEN), when set, enables the ECGON bit to be set. ECGON turns on the external clock input path through the PTE4/OSC1 pin. When EXTCLKEN is clear, ECGON cannot be set and PTE4/OSC1 will always perform the PTE4 function. The default state for this option is clear.
7.6.2 External Crystal Enable (EXTXTALEN)
External crystal enable (EXTXTALEN), when set, will enable an amplifier to drive the PTE3/OSC2 pin from the PTE4/OSC1 pin. The amplifier will drive only if the external clock enable (EXTCLKEN) bit and the ECGON bit are also set. If EXTCLKEN or ECGON are clear, PTE3/OSC2 will perform the PTE3 function. When EXTXTALEN is clear, PTE3/OSC2 will always perform the PTE3 function. EXTXTALEN, when set, also configures the clock monitor to expect an external clock source in the valid range of crystals (30 kHz to 100 kHz or 1 MHz to 8 MHz). When EXTXTALEN is clear, the clock monitor will expect an external clock source in the valid range for externally generated clocks when using the clock monitor (60 Hz to 32 MHz). EXTXTALEN, when set, also configures the external clock stabilization divider in the clock monitor for a 4096 cycle timeout to allow the proper stabilization time for a crystal. When EXTXTALEN is clear, the stabilization divider is configured to 16 cycles since an external clock source does not need a startup time. The default state for this option is clear.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 93
Internal Clock Generator (ICG) Module)
7.6.3 Slow External Clock (EXTSLOW)
Slow external clock (EXTSLOW), when set, will decrease the drive strength of the oscillator amplifier, enabling low-frequency crystal operation (30 kHz-100 kHz) if properly enabled with the external clock enable (EXTCLKEN) and external crystal enable (EXTXTALEN) bits. When clear, EXTSLOW enables high-frequency crystal operation (1 MHz to 8 MHz). EXTSLOW, when set, also configures the clock monitor to expect an external clock source that is slower than the low-frequency base clock (60 Hz to 307.2 kHz). When EXTSLOW is clear, the clock monitor will expect an external clock faster than the low-frequency base clock (307.2 kHz to 32 MHz). The default state for this option is clear.
7.6.4 Oscillator Enable In Stop (OSCENINSTOP)
Oscillator enable in stop (OSCENINSTOP), when set, will enable the ICG to continue to generate clocks (either CGMXCLK, CGMOUT, COPCLK, or TBMCLK) in stop mode. This function is used to keep the timebase and COP running while the rest of the microcontroller stops. The clock monitor and autoswitching functions remain operative. When OSCENINSTOP is clear, all clock generation will cease and CGMXCLK, CGMOUT, COPCLK, and TBMCLK will be forced low during stop mode. The clock monitor and autoswitching functions become inoperative. The default state for this option is clear.
7.7 Input/Output (I/O) Registers
The ICG contains five registers, summarized in Figure 7-11. These registers are: 1. ICG control register (ICGCR) 2. ICG multiplier register (ICGMR) 3. ICG trim register (ICGTR) 4. ICG DCO divider control register (ICGDVR) 5. ICG DCO stage control register (ICGDSR) Several of the bits in these registers have interaction where the state of one bit may force another bit to a particular state or prevent another bit from being set or cleared. A summary of this interaction is shown in Table 7-4.
6 CMF ICG Control Register Read: CMIE $0036 (ICGCR) Write: 0(1) See page 96. Reset: 0 0 1. See 7.7.1 ICG Control Register for method of clearing the CMF bit. ICG Multiply Register Read: (ICGMR) Write: See page 97. Reset: N6 0 0 = Unimplemented Addr. Register Name Bit 7 5 CMON 0 4 CS 0 3 ICGON 1 2 ICGS 0 1 ECGON 0 Bit 0 ECGS 0
$0037
N5 0
N4 1 R
N3 0 = Reserved
N2 1
N1 0 U = Unaffected
N0 1
Figure 7-11. ICG Module I/O Register Summary
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 94 Freescale Semiconductor
Input/Output (I/O) Registers Addr. $0038 Register Name ICG Trim Register Read: (ICGTR) Write: See page 98. Reset: ICG Divider Control Read: Register (ICGDVR) Write: See page 98. Reset: ICG DCO Stage Control Read: Register (ICGDSR) Write: See page 98. Reset: Bit 7 TRIM7 1 6 TRIM6 0 5 TRIM5 0 4 TRIM4 0 3 TRIM3 0 DDIV3 0 DSTG7 R 0 DSTG6 R 0 DSTG5 R 0 U 2 TRIM2 0 DDIV2 U DSTG2 R 1 TRIM1 0 DDIV1 U DSTG1 R Bit 0 TRIM0 0 DDIV0 U DSTG0 R
$0039
$003A
DSTG4 DSTG3 R R Unaffected by reset R = Reserved
= Unimplemented
U = Unaffected
Figure 7-11. ICG Module I/O Register Summary (Continued)
Table 7-4. ICG Module Register Bit Interaction Summary
Register Bit Results for Given Condition CMIE ICGS CMF Condition DSTG[7:0] -- -- uw uw -- uw uw -- -- uw -- uw -- uw uw -- -- 95 TRIM[7:0] DDIV[3:0] -- -- uw uw -- uw uw -- -- uw -- uw -- uw uw -- -- ECGON ICGON CMON ECGS N[6:0] $15 -- -- uw -- uw -- -- -- -- -- -- -- uw uw -- --
Reset OSCENINSTOP = 0, STOP = 1 EXTCLKEN = 0 CMF = 1 CMON = 0 CMON = 1 CS = 0 CS = 1 ICGON = 0 ICGON = 1 ICGS = 0 ECGON = 0 ECGS = 0 IOFF = 1 EOFF = 1 N = written TRIM = written
0 0 0 -- 0 -- -- -- 0 -- us 0 us -- -- (0) (0)
0 0 0 (1) 0 -- -- -- 0 -- -- 0 -- 1* 1* (0) (0)
0 0 0 1 (0) (1) -- -- 0 -- us 0 us (1) (1) (0) (0)
CS 0 -- 0 -- -- -- (0) (1) 1 -- uc 0 us 1 0 -- --
1 -- 1 1 -- 1 1 -- (0) (1) -- 1 -- (1) (1) -- --
0 0 -- -- -- -- -- -- 0 -- (0) -- -- 0 -- 0* 0*
0 -- 0 1 -- 1 -- 1 1 -- -- (0) -- (1) (1) -- --
0 0 0 -- -- -- -- -- -- -- -- 0 (0) -- 0 -- --
$80 -- -- uw -- uw -- -- -- -- -- -- -- uw uw -- --
-- 0, 1 0*, 1* (0), (1) us, uc, uw
Register bit is unaffected by the given condition. Register bit is forced clear or set (respectively) in the given condition. Register bit is temporarily forced clear or set (respectively) in the given condition. Register bit must be clear or set (respectively) for the given condition to occur. Register bit cannot be set, cleared, or written (respectively) in the given condition.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor
Internal Clock Generator (ICG) Module)
7.7.1 ICG Control Register
The ICG control register (ICGCR) contains the control and status bits for the internal clock generator, external clock generator, and clock monitor as well as the clock select and interrupt enable bits.
Address: $0036 Bit 7 Read: Write: Reset: CMIE 0 6 CMF 0(1) 0 5 CMON 0 4 CS 0 3 ICGON 1 2 ICGS 0 1 ECGON 0 Bit 0 ECGS 0
1. See CMF bit description for method of clearing CMF bit. = Unimplemented
Figure 7-12. ICG Control Register (ICGCR) CMIE -- Clock Monitor Interrupt Enable Bit This read/write bit enables clock monitor interrupts. An interrupt will occur when both CMIE and CMF are set. CMIE can be set when the CMON bit has been set for at least one cycle. CMIE is forced clear when CMON is clear or during reset. 1 = Clock monitor interrupts enabled 0 = Clock monitor interrupts disabled CMF -- Clock Monitor Interrupt Flag This read-only bit is set when the clock monitor determines that either ICLK or ECLK becomes inactive and the CMON bit is set. This bit is cleared by first reading the bit while it is set, followed by writing the bit low. This bit is forced clear when CMON is clear or during reset. 1 = Either ICLK or ECLK has become inactive. 0 = ICLK and ECLK have not become inactive since the last read of the ICGCR, or the clock monitor is disabled. CMON -- Clock Monitor On Bit This read/write bit enables the clock monitor. CMON can be set when both ICLK and ECLK have been on and stable for at least one bus cycle. (ICGON, ECGON, ICGS, and ECGS are all set.) CMON is forced set when CMF is set, to avoid inadvertent clearing of CMF. CMON is forced clear when either ICGON or ECGON is clear, during stop mode with OSCENINSTOP low, or during reset. 1 = Clock monitor output enabled 0 = Clock monitor output disabled CS -- Clock Select Bit This read/write bit determines which clock will generate the oscillator output clock (CGMXCLK). This bit can be set when ECGON and ECGS have been set for at least one bus cycle and can be cleared when ICGON and ICGS have been set for at least one bus cycle. This bit is forced set when the clock monitor determines the internal clock (ICLK) is inactive or when ICGON is clear. This bit is forced clear when the clock monitor determines that the external clock (ECLK) is inactive, when ECGON is clear, or during reset. 1 = External clock (ECLK) sources CGMXCLK 0 = Internal clock (ICLK) sources CGMXCLK
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 96 Freescale Semiconductor
Input/Output (I/O) Registers
ICGON -- Internal Clock Generator On Bit This read/write bit enables the internal clock generator. ICGON can be cleared when the CS bit has been set and the CMON bit has been clear for at least one bus cycle. ICGON is forced set when the CMON bit is set, the CS bit is clear, or during reset. 1 = Internal clock generator enabled 0 = Internal clock generator disabled ICGS -- Internal Clock Generator Stable Bit This read-only bit indicates when the internal clock generator has determined that the internal clock (ICLK) is within about 5 percent of the desired value. This bit is forced clear when the clock monitor determines the ICLK is inactive, when ICGON is clear, when the ICG multiplier register (ICGMR) is written, when the ICG TRIM register (ICGTR) is written, during stop mode with OSCENINSTOP low, or during reset. 1 = Internal clock is within 5 percent of the desired value. 0 = Internal clock may not be within 5 percent of the desired value. ECGON -- External Clock Generator On Bit This read/write bit enables the external clock generator. ECGON can be cleared when the CS and CMON bits have been clear for at least one bus cycle. ECGON is forced set when the CMON bit or the CS bit is set. ECGON is forced clear during reset. 1 = External clock generator enabled 0 = External clock generator disabled ECGS -- External Clock Generator Stable Bit This read-only bit indicates when at least 4096 external clock (ECLK) cycles have elapsed since the external clock generator was enabled. This is not an assurance of the stability of ECLK but is meant to provide a startup delay. This bit is forced clear when the clock monitor determines ECLK is inactive, when ECGON is clear, during stop mode with OSCENINSTOP low, or during reset. 1 = 4096 ECLK cycles have elapsed since ECGON was set. 0 = External clock is unstable, inactive, or disabled.
7.7.2 ICG Multiplier Register
Address: $0037 Bit 7 Read: Write: Reset: 0 6 N6 0 = Unimplemented 5 N5 0 4 N4 1 3 N3 0 2 N2 1 1 N1 0 Bit 0 N0 1
Figure 7-13. ICG Multiplier Register (ICGMR) N6:N0 -- ICG Multiplier Factor Bits These read/write bits change the multiplier used by the internal clock generator. The internal clock (ICLK) will be: (307.2 kHz 25 percent) * N A value of $00 in this register is interpreted the same as a value of $01. This register cannot be written when the CMON bit is set. Reset sets this factor to $15 (decimal 21) for default frequency of 6.45 MHz 25 percent (1.613 MHz 25 percent bus).
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 97
Internal Clock Generator (ICG) Module)
7.7.3 ICG Trim Register
Address: $0038 Bit 7 Read: TRIM7 Write: Reset: 1 6 TRIM6 0 5 TRIM5 0 4 TRIM4 0 3 TRIM3 0 2 TRIM2 0 1 TRIM1 0 Bit 0 TRIM0 0
Figure 7-14. ICG Trim Register (ICGTR) TRIM7:TRIM0 -- ICG Trim Factor Bits These read/write bits change the size of the internal capacitor used by the internal clock generator. By testing the frequency of the internal clock and incrementing or decrementing this factor accordingly, the accuracy of the internal clock can be improved to 2 percent. Incrementing this register by one decreases the frequency by 0.195 percent of the unadjusted value. Decrementing this register by one increases the frequency by 0.195 percent. This register cannot be written when the CMON bit is set. Reset sets these bits to $80, centering the range of possible adjustment.
7.7.4 ICG DCO Divider Register
Address: $0039 Bit 7 Read: Write: Reset: 0 6 5 4 3 DDIV3 U U = Unaffected 2 DDIV2 U 1 DDIV1 U Bit 0 DDIV0 U
0 0 = Unimplemented
0
Figure 7-15. ICG DCO Divider Control Register (ICGDVR) DDIV3:DDIV0 -- ICG DCO Divider Control Bits These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator. When ICGON is set, DDIV is controlled by the digital loop filter. The range of valid values for DDIV is from $0 to $9. Values of $A through $F are interpreted the same as $9. Since the DCO is active during reset, reset has no effect on DSTG and the value may vary.
7.7.5 ICG DCO Stage Register
Address: $003A Bit 7 Read: DSTG7 Write: R Reset: R 6 DSTG6 R = Reserved 5 DSTG5 R 4 3 DSTG4 DSTG3 R R Unaffected by reset 2 DSTG2 R 1 DSTG1 R Bit 0 DSTG0 R
Figure 7-16. ICG DCO Stage Control Register (ICGDSR) DSTG7:DSTG0 -- ICG DCO Stage Control Bits These bits indicate the number of stages (above the minimum) in the digitally controlled oscillator. The total number of stages is approximately equal to $1FF, so changing DSTG from $00 to $FF will approximately double the period. Incrementing DSTG will increase the period (decrease the frequency) by 0.202 percent to 0.368 percent (decrementing has the opposite effect). DSTG cannot be written when ICGON is set to prevent inadvertent frequency shifting. When ICGON is set, DSTG is controlled by the digital loop filter. Since the DCO is active during reset, reset has no effect on DSTG and the value may vary.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 98 Freescale Semiconductor
Chapter 8 External Interrupt (IRQ)
8.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
8.2 Features
Features of the IRQ module include: * A dedicated external interrupt pin (IRQ) * IRQ interrupt control bits * Hysteresis buffer * Programmable edge-only or edge and level interrupt sensitivity * Automatic interrupt acknowledge * Internal pullup resistor
8.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a central processor unit (CPU) interrupt request. Figure 8-2 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. * Software clear -- Software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (INTSCR). Writing a 1 to the ACK bit clears the IRQ latch. * Reset -- A reset automatically clears the interrupt latch. The external interrupt pin is falling-edge triggered and is software-configurable to be either falling-edge or falling-edge and low-level triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, software clear, or reset occurs. When an interrupt pin is both falling-edge and low-level triggered, the interrupt remains set until both of these events occur: * Vector fetch or software clear * Return of the interrupt pin to logic 1
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 99
External Interrupt (IRQ)
INTERNAL BUS PORTA M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(3) SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA SERIAL PERIPHERAL INTERFACE MODULE PORTB DDRB PTA7/KBD7- PTA0/KBD0(1) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1)(2) PTC3(1)(2) PTC2(1)(2) PTC1(1)(2) PTC0(1)(2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE2 PTE1/RxD PTE0/TxD
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH MC68HC908GT16 -- 15,872 BYTES MC68HC908GT8 -- 7,680 BYTES USER RAM -- 512 BYTES MONITOR ROM -- 304 BYTES FLASH PROGRAMMING ROUTINES ROM -- 720 BYTES USER FLASH VECTOR SPACE -- 36 BYTES
PTE4/OSC1 PTE3/OSC2
INTERNAL CLOCK GENERATOR MODULE
IRQ(3) VREFH VREFL
MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE
PORTE
MONITOR MODULE DDRE
PORTD
DDRD
PORTC
DDRC
SECURITY MODULE
POWER
MONITOR MODE ENTRY MODULE
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
Figure 8-1. Block Diagram Highlighting IRQ Block and Pins
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 100 Freescale Semiconductor
IRQ Pin
RESET ACK INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE IRQ VDD D CLR Q SYNCHRONIZER CK IRQF IRQ INTERRUPT REQUEST TO CPU FOR BIL/BIH INSTRUCTIONS
IMASK
MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC
Figure 8-2. IRQ Module Block Diagram The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. NOTE The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests.
Addr. $001D Register Name IRQ Status and Control Read: Register (INTSCR) Write: See page 102. Reset: Bit 7 0 0 6 0 0 = Unimplemented 5 0 0 4 0 0 3 IRQF 0 2 0 ACK 0 1 IMASK 0 Bit 0 MODE 0
Figure 8-3. IRQ I/O Register Summary
8.4 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a 1 to the ACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 101
External Interrupt (IRQ)
*
IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ pin to logic 1 -- As long as the IRQ pin is at logic 0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin. NOTE When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine.
8.5 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during the break state. See Chapter 19 Development Support. To allow software to clear the IRQ latch during a break interrupt, write a 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect CPU interrupt flags during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags.
8.6 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: * Shows the state of the IRQ flag * Clears the IRQ latch * Masks IRQ interrupt request * Controls triggering sensitivity of the IRQ interrupt pin
Address: Read: Write: Reset: $001D Bit 7
6
5
4
3 IRQF 0
0
0 0 = Unimplemented
0
2 0 ACK 0
1 IMASK 0
Bit 0 MODE 0
Figure 8-4. IRQ Status and Control Register (INTSCR)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 102 Freescale Semiconductor
IRQ Status and Control Register
IRQF -- IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 103
External Interrupt (IRQ)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 104 Freescale Semiconductor
Chapter 9 Keyboard Interrupt Module (KBI)
9.1 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0-PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup device is also enabled on the pin.
9.2 Features
Features include: * Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask * Hysteresis buffers * Programmable edge-only or edge- and level- interrupt sensitivity * Exit from low-power modes * I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s)
9.3 Functional Description
Writing to the KBIE7-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. * If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 105
Keyboard Interrupt Module (KBI)
INTERNAL BUS PORTA M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(3) SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA SERIAL PERIPHERAL INTERFACE MODULE PORTB DDRB PTA7/KBD7- PTA0/KBD0(1) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1)(2) PTC3(1)(2) PTC2(1)(2) PTC1(1)(2) PTC0(1)(2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE2 PTE1/RxD PTE0/TxD
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH MC68HC908GT16 -- 15,872 BYTES MC68HC908GT8 -- 7,680 BYTES USER RAM -- 512 BYTES MONITOR ROM -- 304 BYTES FLASH PROGRAMMING ROUTINES ROM -- 720 BYTES USER FLASH VECTOR SPACE -- 36 BYTES
PTE4/OSC1 PTE3/OSC2
INTERNAL CLOCK GENERATOR MODULE
IRQ(3) VREFH VREFL
MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE
PORTE
MONITOR MODULE DDRE
PORTD
DDRD
PORTC
DDRC
SECURITY MODULE
POWER
MONITOR MODE ENTRY MODULE
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
Figure 9-1. Block Diagram Highlighting KBI Block and Pins
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 106 Freescale Semiconductor
Functional Description
INTERNAL BUS
ACKK KBD0 VDD TO PULLUP ENABLE KB0IE . KBD7 IMASKK . . D CLR Q RESET
VECTOR FETCH DECODER
KEYF SYNCHRONIZER CK KEYBOARD INTERRUPT REQUEST
TO PULLUP ENABLE KB7IE
MODEK
Figure 9-2. Keyboard Module Block Diagram
Addr. Register Name Keyboard Status Read: and Control Register Write: (INTKBSCR) See page 109. Reset: Keyboard Interrupt Enable Read: Register Write: (INTKBIER) See page 110. Reset: Bit 7 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 KBIE7 0 0 KBIE6 0 = Unimplemented 0 KBIE5 0 0 KBIE4 0 0 KBIE3 0 0 KBIE2 0 1 IMASKK 0 KBIE1 0 Bit 0 MODEK 0 KBIE0 0
$001A
$001B
Figure 9-3. I/O Register Summary If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a 1 to the ACKK bit in the keyboard status and control register (INTKBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. * Return of all enabled keyboard interrupt pins to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 107
Keyboard Interrupt Module (KBI)
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. NOTE Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a 0 for software to read the pin.
9.4 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A. 2. Write 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
9.5 Low-Power Modes
The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes.
9.5.1 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 108 Freescale Semiconductor
Keyboard Module During Break Interrupts
9.5.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
9.6 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. See 9.7.1 Keyboard Status and Control Register.
9.7 I/O Registers
These registers control and monitor operation of the keyboard module: * Keyboard status and control register (INTKBSCR) * Keyboard interrupt enable register (INTKBIER)
9.7.1 Keyboard Status and Control Register
The keyboard status and control register: * Flags keyboard interrupt requests * Acknowledges keyboard interrupt requests * Masks keyboard interrupt requests * Controls keyboard interrupt triggering sensitivity
Address: $001A Bit 7 Read: Write: Reset: 0 0 0 0 0 = Unimplemented 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 1 IMASKK 0 Bit 0 MODEK 0
Figure 9-4. Keyboard Status and Control Register (INTKBSCR) Bits 7-4 -- Not used These read-only bits always read as 0s. KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 109
Keyboard Interrupt Module (KBI)
ACKK -- Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as 0. Reset clears ACKK. IMASKK -- Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
9.7.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin
.
Address: $001B Bit 7 Read: Write: Reset: KBIE7 0 6 KBIE6 0 5 KBIE5 0 4 KBIE4 0 3 KBIE3 0 2 KBIE2 0 1 KBIE1 0 Bit 0 KBIE0 0
Figure 9-5. Keyboard Interrupt Enable Register (INTKBIER) KBIE7-KBIE0 -- Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 110 Freescale Semiconductor
Chapter 10 Low-Voltage Inhibit (LVI)
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.
10.2 Features
Features of the LVI module include: * Programmable LVI reset * Selectable LVI trip voltage * Programmable stop mode operation
10.3 Functional Description
Figure 10-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below a voltage, VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, VTRIPF, to be configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, VTRIPF, to be configured for 3-V operation. The actual trip points are shown in Chapter 20 Electrical Specifications. NOTE After a power-on reset (POR) the LVI's default mode of operation is 3 V. If a 5-V system is used, the user must set the LVI5OR3 bit to raise the trip point to 5-V operation. Note that this must be done after every power-on reset since the default will revert back to 3-V mode after each power-on reset. If the VDD supply is below the 5-V mode trip voltage but above the 3-V mode trip voltage when POR is released, the part will operate because VTRIPF defaults to 3-V mode after a POR. So, in a 5-V system care must be taken to ensure that VDD is above the 5-V mode trip voltage after POR is released. If the user requires 5-V mode and sets the LVI5OR3 bit after a power-on reset while the VDD supply is not above the VTRIPR for 5-V mode, the microcontroller unit (MCU) will immediately go into reset. The LVI in this case will hold the part in reset until either VDD goes above the rising 5-V trip point, VTRIPR, which will release reset or VDD decreases to approximately 0 V which will re-trigger the power-on reset and reset the trip point to 3-V operation.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 111
Low-Voltage Inhibit (LVI)
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See Figure 4-2. Configuration Register 1 (CONFIG1) for details of the LVI's configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 15.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
VDD STOP INSTRUCTION LVISTOP FROM CONFIG1 FROM CONFIG1 LVIRSTD LVIPWRD FROM CONFIG LOW VDD DETECTOR VDD > LVITrip = 0 VDD LVITrip = 1 LVIOUT LVI5OR3 FROM CONFIG1 LVI RESET
Figure 10-1. LVI Module Block Diagram
Addr. $FE0C Register Name LVI Status Register Read: (LVISR) Write: See page 113. Reset: Bit 7 LVIOUT 0 6 0 0 = Unimplemented 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
Figure 10-2. LVI I/O Register Summary
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at 0 to enable the LVI module, and the LVIRSTD bit must be at 1 to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the LVIPWRD and LVIRSTD bits must be at 0 to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 112 Freescale Semiconductor
LVI Status Register
continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS.
10.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V protection. NOTE The microcontroller is guaranteed to operate at a minimum supply voltage. The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than this. (See Chapter 20 Electrical Specifications for the actual trip point voltages.)
10.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level.
Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 $FE0C Bit 7 LVIOUT 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0
Figure 10-3. LVI Status Register (LVISR) LVIOUT -- LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage (see Table 10-1). Reset clears the LVIOUT bit. Table 10-1. LVIOUT Bit Indication
VDD VDD > VTRIPR VDD < VTRIPF VTRIPF < VDD < VTRIPR LVIOUT 0 1 Previous value
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
10.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 113
Low-Voltage Inhibit (LVI)
10.6.2 Stop Mode
If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 114 Freescale Semiconductor
Chapter 11 Low-Power Modes (MODES)
11.1 Introduction
The microcontroller (MCU) may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in the low-power modes.
11.1.1 Wait Mode
The WAIT instruction puts the MCU in a low-power standby mode in which the central processor unit (CPU) clock is disabled but the bus clock continues to run. Power consumption can be further reduced by disabling the LVI module and/or the timebase module through bits in the CONFIG1 register. (See Chapter 4 Configuration Register (CONFIG).)
11.1.2 Stop Mode
Stop mode is entered when a STOP instruction is executed. The CPU clock is disabled and the bus clock is disabled if the OSCENINSTOP bit in the CONFIG2 register is at a 0. (See Chapter 4 Configuration Register (CONFIG).)
11.2 Analog-to-Digital Converter (ADC)
11.2.1 Wait Mode
The analog-to-digital converter (ADC) continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4-ADCH0 bits in the ADC status and control register before executing the WAIT instruction.
11.2.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry.
11.3 Break Module (BRK)
11.3.1 Wait Mode
If enabled, the break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 115
Low-Power Modes (MODES)
11.3.2 Stop Mode
The break module is inactive in stop mode. A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. The STOP instruction does not affect break module register states.
11.4 Central Processor Unit (CPU)
11.4.1 Wait Mode
The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. * Disables the CPU clock
11.4.2 Stop Mode
The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. * Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
11.5 Internal Clock Generator Module (ICG)
11.5.1 Wait Mode
The internal clock generator (ICG) module remains active in wait mode. If enabled, the ICG interrupt to the CPU can bring the MCU out of wait mode. In some applications, low power-consumption is desired in wait mode and a high-frequency clock is not needed. In these applications, reduce power consumption by either selecting a low-frequency external clock and turn the internal clock generator off or reduce the bus frequency by minimizing the ICG multiplier factor (N) before executing the WAIT instruction.
11.5.2 Stop Mode
The value of the oscillator enable in stop (OSCENINSTOP) bit in the CONFIG2 register determines the behavior of the ICG in stop mode. If OSCENINSTOP is low, the ICG is disabled in stop and, upon execution of the STOP instruction, all ICG activity will cease and the output clocks (CGMXCLK, CGMOUT, COPCLK, and TBMCLK) will be held low. Power consumption will be minimal. If OSCENINSTOP is high, the ICG is enabled in stop and activity will continue. This is useful if the timebase module (TBM) is required to bring the MCU out of stop mode. ICG interrupts will not bring the MCU out of stop mode in this case. During stop mode, if OSCENINSTOP is low, several functions in the ICG are affected. The stable bits (ECGS and ICGS) are cleared, which will enable the external clock stabilization divider upon recovery. The clock monitor is disabled (CMON = 0) which will also clear the clock monitor interrupt enable (CMIE) and clock monitor flag (CMF) bits. The CS, ICGON, ECGON, N, TRIM, DDIV, and DSTG bits are unaffected.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 116 Freescale Semiconductor
Computer Operating Properly Module (COP)
11.6 Computer Operating Properly Module (COP)
11.6.1 Wait Mode
The computer operating properly (COP) module remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.
11.6.2 Stop Mode
Stop mode turns off the COPCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the CONFIG1 register enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit.
11.7 External Interrupt Module (IRQ)
11.7.1 Wait Mode
The external interrupt (IRQ) module remains active in wait mode. Clearing the IMASK1 bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of wait mode.
11.7.2 Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK1 bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of stop mode.
11.8 Keyboard Interrupt Module (KBI)
11.8.1 Wait Mode
The keyboard interrupt (KBI) module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
11.8.2 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
11.9 Low-Voltage Inhibit Module (LVI)
11.9.1 Wait Mode
If enabled, the low-voltage inhibit (LVI) module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 117
Low-Power Modes (MODES)
11.9.2 Stop Mode
If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
11.10 Enhanced Serial Communications Interface Module (SCI)
11.10.1 Wait Mode
The enhanced serial communications interface (ESCI), or SCI module for short, module remains active in wait mode. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction.
11.10.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data.
11.11 Serial Peripheral Interface Module (SPI)
11.11.1 Wait Mode
The serial peripheral interface (SPI) module remains active in wait mode. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction.
11.11.2 Stop Mode
The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset.
11.12 Timer Interface Module (TIM1 and TIM2)
11.12.1 Wait Mode
The timer interface modules (TIM) remain active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 118 Freescale Semiconductor
Timebase Module (TBM)
11.12.2 Stop Mode
The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
11.13 Timebase Module (TBM)
11.13.1 Wait Mode
The timebase module (TBM) remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, reduce the power consumption by stopping the timebase before enabling the WAIT instruction.
11.13.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been enabled to operate during stop mode through the OSCENINSTOP bit in the CONFIG2 register. The timebase module can be used in this mode to generate a periodic wakeup from stop mode. If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. In stop mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the STOP instruction.
11.14 Exiting Wait Mode
These events restart the CPU clock and load the program counter with the reset vector or with an interrupt vector: * External reset -- A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. * External interrupt -- A high-to-low transition on an external interrupt pin (IRQ pin) loads the program counter with the contents of locations: $FFFA and $FFFB; IRQ pin. * Break interrupt -- A break interrupt loads the program counter with the contents of $FFFC and $FFFD. * Computer operating properly module (COP) reset -- A timeout of the COP counter resets the MCU and loads the program counter with the contents of $FFFE and $FFFF. * Low-voltage inhibit module (LVI) reset -- A power supply voltage below the VTRIPF voltage resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. * Internal Clock Generator module (ICG) interrupt -- A CPU interrupt request from the ICG loads the program counter with the contents of $FFF8 and $FFF9. * Keyboard module (KBI) interrupt -- A CPU interrupt request from the KBI module loads the program counter with the contents of $FFE0 and $FFE1. * Timer 1 interface module (TIM1) interrupt -- A CPU interrupt request from the TIM1 loads the program counter with the contents of: - $FFF2 and $FFF3; TIM1 overflow - $FFF4 and $FFF5; TIM1 channel 1 - $FFF6 and $FFF7; TIM1 channel 0
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 119
Low-Power Modes (MODES)
*
*
*
* *
Timer 2 interface module (TIM2) interrupt -- A CPU interrupt request from the TIM2 loads the program counter with the contents of: - $FFEC and $FFED; TIM2 overflow - $FFEE and $FFEF; TIM2 channel 1 - $FFF0 and $FFF1; TIM2 channel 0 Serial peripheral interface module (SPI) interrupt -- A CPU interrupt request from the SPI loads the program counter with the contents of: - $FFE8 and $FFE9; SPI transmitter - $FFEA and $FFEB; SPI receiver Serial communications interface module (SCI) interrupt -- A CPU interrupt request from the SCI loads the program counter with the contents of: - $FFE2 and $FFE3; SCI transmitter - $FFE4 and $FFE5; SCI receiver - $FFE6 and $FFE7; SCI receiver error Analog-to-digital converter module (ADC) interrupt -- A CPU interrupt request from the ADC loads the program counter with the contents of: $FFDE and $FFDF; ADC conversion complete. Timebase module (TBM) interrupt -- A CPU interrupt request from the TBM loads the program counter with the contents of: $FFDC and $FFDD; TBM interrupt.
11.15 Exiting Stop Mode
These events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: * External reset -- A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. * External interrupt -- A high-to-low transition on an external interrupt pin loads the program counter with the contents of locations: - $FFFA and $FFFB; IRQ pin - $FFE0 and $FFE1; keyboard interrupt pins * Low-voltage inhibit (LVI) reset -- A power supply voltage below the LVITRIPF voltage resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. * Break interrupt -- A break interrupt loads the program counter with the contents of locations $FFFC and $FFFD. * Timebase module (TBM) interrupt -- A TBM interrupt loads the program counter with the contents of locations $FFDC and $FFDD when the timebase counter has rolled over. This allows the TBM to generate a periodic wakeup from stop mode. Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt. The short stop recovery bit, SSREC, in the CONFIG1 register controls the oscillator stabilization delay during stop recovery. Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. NOTE Use the full stop recovery time (SSREC = 0) in applications that use an external crystal.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 120 Freescale Semiconductor
Chapter 12 Input/Output (I/O) Ports (PORTS)
12.1 Introduction
Bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with pullup devices if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
Addr. Register Name Read: Port A Data Register (PTA) Write: See page 124. Reset: Read: Port B Data Register (PTB) Write: See page 126. Reset: Read: Port C Data Register (PTC) Write: See page 128. Reset: Read: Port D Data Register (PTD) Write: See page 130. Reset: Read: Data Direction Register A (DDRA) Write: See page 124. Reset: Read: Data Direction Register B (DDRB) Write: See page 126. Reset: Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
$0000
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
$0002
Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset DDRA7 0 DDRB7 0 DDRA6 0 DDRB6 0 = Unimplemented DDRA5 0 DDRB5 0 DDRA4 0 DDRB4 0 DDRA3 0 DDRB3 0 DDRA2 0 DDRB2 0 DDRA1 0 DDRB1 0 DDRA0 0 DDRB0 0
$0004
$0005
Figure 12-1. I/O Port Register Summary
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 121
Input/Output (I/O) Ports (PORTS) Addr. Register Name Read: Data Direction Register C (DDRC) Write: See page 128. Reset: Read: Data Direction Register D (DDRD) Write: See page 131. Reset: Read: Port E Data Register (PTE) Write: See page 133. Reset: Read: Data Direction Register E (DDRE) Write: See page 134. Reset: Bit 7 0 DDRC6 0 DDRD7 0 0 0 DDRD6 0 0 DDRC5 0 DDRD5 0 0 PTE4 PTE3 PTE2 PTE1 PTE0 DDRC4 0 DDRD4 0 DDRC3 0 DDRD3 0 DDRC2 0 DDRD2 0 DDRC1 0 DDRD1 0 DDRC0 0 DDRD0 0 6 5 4 3 2 1 Bit 0
$0006
$0007
$0008
Unaffected by reset 0 0 0 DDRE4 0 0 PTAPUE6 0 PTCPUE6 0 0 PTDPUE6 0 = Unimplemented 0 PTAPUE5 0 PTCPUE5 0 PTDPUE5 0 0 PTAPUE4 0 PTCPUE4 0 PTDPUE4 0 DDRE3 0 PTAPUE3 0 PTCPUE3 0 PTDPUE3 0 DDRE2 0 PTAPUE2 0 PTCPUE2 0 PTDPUE2 0 DDRE1 0 PTAPUE1 0 PTCPUE1 0 PTDPUE1 0 DDRE0 0 PTAPUE0 0 PTCPUE0 0 PTDPUE0 0
$000C
$000D
Read: Port A Input Pullup Enable PTAPUE7 Register (PTAPUE) Write: See page 125. Reset: 0 Read: Port C Input Pullup Enable Register (PTCPUE) Write: See page 129. Reset: 0
$000E
$000F
Read: Port D Input Pullup Enable PTDPUE7 Register (PTDPUE) Write: See page 132. Reset: 0
Figure 12-1. I/O Port Register Summary (Continued)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 122 Freescale Semiconductor
Introduction
Table 12-1. Port Control Register Bits Summary
Port Bit 0 1 2 A 3 4 5 6 7 0 1 2 B 3 4 5 6 7 0 1 2 C 3 4 5 6 0 1 2 D 3 4 5 6 7 0 1 E 2 3 4 DDR DDRA0 DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 DDRA6 DDRA7 DDRB0 DDRB1 DDRB2 DDRB3 DDRB4 DDRB5 DDRB6 DDRB7 DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRD0 DDRD1 DDRD2 DDRD3 DDRD4 DDRD5 DDRD6 DDRD7 DDRE0 DDRE1 DDRE2 DDRE3 DDRE4 ICG ECGON: EXTXTALEN ECGON TIM1 TIM2 SCI ELS0B:ELS0A ELS1B:ELS1A ELS0B:ELS0A ELS1B:ELS1A ENSCI SPI SPE ADC ADCH4-ADCH0 KBD Module Control KBIE0 KBIE1 KBIE2 KBIE3 KBIE4 KBIE5 KBIE6 KBIE7 Pin PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 PTA5/KBD5 PTA6/KBD6 PTA7/KBD7 PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6 PTB7/AD7 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK PTD4/T1CH0 PTD5/T1CH1 PTD6/T2CH0 PTD7/T2CH1 PTE0/TxD PTE1/RxD PTE2 PTE3/OSC2 PTE4/OSC1
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 123
Input/Output (I/O) Ports (PORTS)
12.2 Port A
Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module. Port A also has software configurable pullup devices if configured as an input port.
12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the eight port A pins.
Address: Read: Write: Reset: Alternative Function: KBD7 KBD6 KBD5 $0000 Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by reset KBD4 KBD3 KBD2 KBD1 KBD0
Figure 12-2. Port A Data Register (PTA) PTA7-PTA0 -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBD7-KBD0 -- Keyboard Inputs The keyboard interrupt enable bits, KBIE7-KBIE0, in the keyboard interrupt control register (KBICR) enable the port A pins as external interrupt pins. See Chapter 9 Keyboard Interrupt Module (KBI).
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
Address: Read: Write: Reset: $0004 Bit 7 DDRA7 0 6 DDRA6 0 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 1 DDRA1 0 Bit 0 DDRA0 0
Figure 12-3. Data Direction Register A (DDRA) DDRA7-DDRA0 -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA7-DDRA0, configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 124 Freescale Semiconductor
Port A
Figure 12-4 shows the port A I/O logic.
VDD READ DDRA ($0004) PTAPUEx WRITE DDRA ($0004) RESET WRITE PTA ($0000) PTAx PTAx DDRAx 45 k
INTERNAL DATA BUS
READ PTA ($0000)
Figure 12-4. Port A I/O Circuit When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-2 summarizes the operation of the port A pins. Table 12-2. Port A Pin Functions
PTAPUE Bit 1 0 X DDRA Bit 0 0 1 PTA Bit X(1) X X I/O Pin Mode Input, VDD(2) Input, Hi-Z(4) Output Accesses to DDRA Read/Write DDRA7-DDRA0 DDRA7-DDRA0 DDRA7-DDRA0 Accesses to PTA Read Pin Pin PTA7-PTA0 Write PTA7-PTA0(3) PTA7-PTA0(3) PTA7-PTA0
1. X = Don't care 2. I/O pin pulled up to VDD by internal pullup device 3. Writing affects data register, but does not affect input. 4. Hi-Z = High impedance
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each of the eight port A pins. Each bit is individually configurable and requires that the data direction register, DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit's DDRA is configured for output mode
.
Address: Read: Write: Reset:
$0004 Bit 7 PTAPUE7 0 6 PTAPUE6 0 5 PTAPUE5 0 4 PTAPUE4 0 3 PTAPUE3 0 2 PTAPUE2 0 1 PTAPUE1 0 Bit 0 PTAPUE0 0
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 125
Input/Output (I/O) Ports (PORTS)
PTAPUE7-PTAPUE0 -- Port A Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected
12.3 Port B
Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (ADC) module.
12.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port pins.
Address: Read: Write: Reset: Alternative Function: AD7 AD6 AD5 $0001 Bit 7 PTB7 6 PTB6 5 PTB5 4 PTB4 3 PTB3 2 PTB2 1 PTB1 Bit 0 PTB0
Unaffected by reset AD4 AD3 AD2 AD1 AD0
Figure 12-6. Port B Data Register (PTB) PTB7-PTB0 -- Port B Data Bits These read/write bits are software-programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. AD7-AD0 -- Analog-to-Digital Input Bits AD7-AD0 are pins used for the input channels to the analog-to-digital converter module. The channel select bits in the ADC status and control register define which port B pin will be used as an ADC input and overrides any control from the port I/O logic by forcing that pin as the input to the analog circuitry. NOTE Care must be taken when reading port B while applying analog voltages to AD7-AD0 pins. If the appropriate ADC channel is not enabled, excessive current drain may occur if analog voltages are applied to the PTBx/ADx pin, while PTB is read as a digital input. Those ports not selected as analog input channels are considered digital I/O ports.
12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
Address: Read: Write: Reset: $0005 Bit 7 DDRB7 0 6 DDRB6 0 5 DDRB5 0 4 DDRB4 0 3 DDRB3 0 2 DDRB2 0 1 DDRB1 0 Bit 0 DDRB0 0
Figure 12-7. Data Direction Register B (DDRB)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 126 Freescale Semiconductor
Port C
DDRB7-DDRB0 -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB7-DDRB0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 12-8 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) PTBx PTBx DDRBx
READ PTB ($0001)
Figure 12-8. Port B I/O Circuit When bit DDRBx is a 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-3 summarizes the operation of the port B pins. Table 12-3. Port B Pin Functions
DDRB Bit 0 1 PTB Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRB Read/Write DDRB7-DDRB0 DDRB7-DDRB0 Read Pin PTB7-PTB0 Accesses to PTB Write PTB7-PTB0(3) PTB7-PTB0
1. X = Don't care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input.
12.4 Port C
Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 127
Input/Output (I/O) Ports (PORTS)
12.4.1 Port C Data Register
The port C data register (PTC) contains a data latch for each of the seven port C pins. NOTE Bit 6 and bit 5 of PTC are not available in the 42-pin shrink dual in-line package.
Address: Read: Write: Reset: = Unimplemented $0002 Bit 7 0 6 PTC6 5 PTC5 4 PTC4 3 PTC3 2 PTC2 1 PTC1 Bit 0 PTC0
Unaffected by reset
Figure 12-9. Port C Data Register (PTC) PTC6-PTC0 -- Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data.
12.4.2 Data Direction Register C
Data direction register C (DDRC) determines whether each port C pin is an input or an output. Writing a 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a 0 disables the output buffer.
Address: Read: Write: Reset: 0 $0006 Bit 7 0 6 DDRC6 0 = Unimplemented 5 DDRC5 0 4 DDRC4 0 3 DDRC3 0 2 DDRC2 0 1 DDRC1 0 Bit 0 DDRC0 0
Figure 12-10. Data Direction Register C (DDRC) DDRC6-DDRC0 -- Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC6-DDRC0, configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 12-11 shows the port C I/O logic. NOTE For those devices packaged in a 42-pin shrink dual in-line package, PTC5 and PTC6 are connected to ground internally. DDRC5 and DDRC6 should be set to a 0 to configure PTC5 and PTC6 as inputs.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 128 Freescale Semiconductor
Port C
VDD PTCPUEx WRITE DDRC ($0006) INTERNAL DATA BUS RESET WRITE PTC ($0002) PTCx PTCx DDRCx 45 k
READ DDRC ($0006)
READ PTC ($0002)
Figure 12-11. Port C I/O Circuit When bit DDRCx is a 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port C pins. Table 12-4. Port C Pin Functions
PTCPUE Bit 1 0 X DDRC Bit 0 0 1 PTC Bit X
(1)
I/O Pin Mode Input, VDD
(2)
Accesses to DDRC Read/Write DDRC6-DDRC0 DDRC6-DDRC0 DDRC6-DDRC0
Accesses to PTC Read Pin Pin PTC6-PTC0 Write PTC6-PTC0(3) PTC6-PTC0(3) PTC6-PTC0
X X
Input, Hi-Z(4) Output
1. X = Don't care 2. I/O pin pulled up to VDD by internal pullup device. 3. Writing affects data register, but does not affect input. 4. Hi-Z = High impedance
12.4.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit's DDRC is configured for output mode.
Address: Read: Write: Reset: 0 $000E Bit 7 0 6 PTCPUE6 0 = Unimplemented 5 PTCPUE5 0 4 PTCPUE4 0 3 PTCPUE3 0 2 PTCPUE2 0 1 PTCPUE1 0 Bit 0 PTCPUE0 0
Figure 12-12. Port C Input Pullup Enable Register (PTCPUE)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 129
Input/Output (I/O) Ports (PORTS)
PTCPUE6-PTCPUE0 -- Port C Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port C pin configured to have internal pullup 0 = Corresponding port C pin internal pullup disconnected
12.5 Port D
Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI) module and four of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software configurable pullup devices if configured as an input port.
12.5.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the eight port D pins.
Address: Read: Write: Reset: Alternative Function: T2CH1 T2CH0 T1CH1 $0003 Bit 7 PTD7 6 PTD6 5 PTD5 4 PTD4 3 PTD3 2 PTD2 1 PTD1 Bit 0 PTD0
Unaffected by reset T1CH0 SPSCK MOSI MISO SS
Figure 12-13. Port D Data Register (PTD) PTD7-PTD0 -- Port D Data Bits These read/write bits are software-programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. T2CH1 and T2CH0 -- Timer 2 Channel I/O Bits The PTD7/T2CH1-PTD6/T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTD7/T2CH1-PTD6/T2CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 18 Timer Interface Module (TIM). T1CH1 and T1CH0 -- Timer 1 Channel I/O Bits The PTD7/T1CH1-PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1-PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 18 Timer Interface Module (TIM). SPSCK -- SPI Serial Clock The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the PTD3/SPSCK pin is available for general-purpose I/O. MOSI -- Master Out/Slave In The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear, the PTD2/MOSI pin is available for general-purpose I/O. MISO -- Master In/Slave Out The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit, SPE, is clear, the SPI module is disabled, and the PTD0/SS pin is available for general-purpose I/O.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 130 Freescale Semiconductor
Port D
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used by the SPI module. However, the DDRD bits always determine whether reading port D returns the states of the latches or the states of the pins. See Table 12-5. SS -- Slave Select The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI is enabled, the DDRB0 bit in data direction register B (DDRB) has no effect on the PTD0/SS pin.
12.5.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
Address: Read: Write: Reset: $0007 Bit 7 DDRD7 0 6 DDRD6 0 5 DDRD5 0 4 DDRD4 0 3 DDRD3 0 2 DDRD2 0 1 DDRD1 0 Bit 0 DDRD0 0
Figure 12-14. Data Direction Register D (DDRD) DDRD7-DDRD0 -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD7-DDRD0, configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 12-15 shows the port D I/O logic.
VDD PTDPUEx WRITE DDRD ($0007) RESET INTERNAL DATA BUS WRITE PTD ($0003) PTDx PTDx DDRDx 30 k
READ DDRD ($0007)
READ PTD ($0003)
Figure 12-15. Port D I/O Circuit
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 131
Input/Output (I/O) Ports (PORTS)
When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-5 summarizes the operation of the port D pins. Table 12-5. Port D Pin Functions
PTDPUE Bit 1 0 X DDRD Bit 0 0 1 PTD Bit X(1) X X I/O Pin Mode Input, VDD(2) Input, Hi-Z(4) Output Accesses to DDRD Read/Write DDRD7-DDRD0 DDRD7-DDRD0 DDRD7-DDRD0 Accesses to PTD Read Pin Pin PTD7-PTD0 Write PTD7-PTD0(3) PTD7-PTD0(3) PTD7-PTD0
1. X = Don't care 2. I/O pin pulled up to VDD by internal pullup device. 3. Writing affects data register, but does not affect input. 4. Hi-Z = High imp[edance
12.5.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each of the eight port D pins. Each bit is individually configurable and requires that the data direction register, DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit's DDRD is configured for output mode.
Address: Read: Write: Reset: $000F Bit 7 PTDPUE7 0 6 PTDPUE6 0 5 PTDPUE5 0 4 PTDPUE4 0 3 PTDPUE3 0 2 PTDPUE2 0 1 PTDPUE1 0 Bit 0 PTDPUE0 0
Figure 12-16. Port D Input Pullup Enable Register (PTDPUE) PTDPUE7-PTDPUE0 -- Port D Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port D pin configured to have internal pullup 0 = Corresponding port D pin has internal pullup disconnected
12.6 Port E
Port E is a 5-bit special-function port that shares two of its pins with the serial communications interface (SCI) module and two of its pins with the internal clock generator (ICG).
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 132 Freescale Semiconductor
Port E
12.6.1 Port E Data Register
The port E data register contains a data latch for each of the five port E pins.
Address: Read: Write: Reset: Alternative Function: = Unimplemented $0008 Bit 7 0 6 0 5 0 4 PTE4 3 PTE3 2 PTE2 1 PTE1 Bit 0 PTE0
Unaffected by reset OSC1 OSC2 RxD TxD
Figure 12-17. Port E Data Register (PTE) PTE4-PTE0 -- Port E Data Bits These read/write bits are software-programmable. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. Reset has no effect on port Edata. NOTE Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Table 12-6. OSC2 and OSC1 -- OSC2 and OSC1 Bits Under software control, PTE4 and PTE3 can be configured as external clock inputs and outputs. PTE3 will become an output clock, OSC2, if selected in the configuration registers and enabled in the ICG registers. PTE4 will become an external input clock source, OSC1, if selected in the configuration registers and enabled in the ICG registers. See Chapter 7 Internal Clock Generator (ICG) Module) and Chapter 5 Computer Operating Properly (COP) Module. While configured as oscillator pins, writes have no effect and reads return undefined values. RxD -- SCI Receive Data Input The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See Chapter 14 Enhanced Serial Communications Interface (ESCI) Module. TxD -- SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See Chapter 14 Enhanced Serial Communications Interface (ESCI) Module.
12.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 133
Input/Output (I/O) Ports (PORTS)
Address: Read: Write: Reset:
$000C Bit 7 0 0 6 0 0 = Unimplemented 5 0 0 4 DDRE4 0 3 DDRE3 0 2 DDRE2 0 1 DDRE1 0 Bit 0 DDRE0 0
Figure 12-18. Data Direction Register E (DDRE) DDRE4-DDRE0 -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE4-DDRE0, configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input NOTE Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 12-19 shows the port E I/O logic.
READ DDRE ($000C)
WRITE DDRE ($000C) INTERNAL DATA BUS RESET WRITE PTE ($0008) PTEx PTEx DDREx
READ PTE ($0008)
Figure 12-19. Port E I/O Circuit When bit DDREx is a 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-6 summarizes the operation of the port E pins. Table 12-6. Port E Pin Functions
DDRE Bit 0 1 PTE Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRE Read/Write DDRE4-DDRE0 DDRE4-DDRE0 Read Pin PTE4-PTE0 Accesses to PTE Write PTE4-PTE0(3) PTE4-PTE0
1. X = Don't care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 134 Freescale Semiconductor
Chapter 13 Resets and Interrupts
13.1 Introduction
Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the MCU to its startup condition. An interrupt vectors the program counter to a service routine.
13.2 Resets
A reset immediately returns the MCU to a known startup condition and begins program execution from a user-defined memory location.
13.2.1 Effects
A reset: * Immediately stops the operation of the instruction being executed * Initializes certain control and status bits * Loads the program counter with a user-defined reset vector address from locations $FFFE and $FFFF * Selects CGMXCLK divided by four as the bus clock
13.2.2 External Reset
A logic 0 applied to the RST pin for a time, tIRL, generates an external reset. An external reset sets the PIN bit in the SIM reset status register.
13.2.3 Internal Reset
Sources: * Power-on reset (POR) * Computer operating properly (COP) * Low-power reset circuits * Illegal opcode * Illegal address All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin. See Figure 13-1.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 135
Resets and Interrupts
PULLED LOW BY MCU RST PIN 32 CYCLES CGMXCLK INTERNAL RESET 32 CYCLES
Figure 13-1. Internal Reset Timing 13.2.3.1 Power-On Reset (POR) A power-on reset (POR) is an internal reset caused by a positive transition on the VDD pin. VDD at the POR must go completely to 0 V to reset the MCU. This distinguishes between a reset and a POR. The POR is not a brown-out detector, low-voltage detector, or glitch detector. A power-on reset: * Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096 CGMXCLK cycles * Drives the RST pin low during the oscillator stabilization delay * Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay * Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay * Sets the POR bit in the SIM reset status register and clears all other bits in the register
OSC1 PORRST(1) 4096 CYCLES CGMXCLK CGMOUT RST PIN INTERNAL RESET 32 CYCLES 32 CYCLES
1. PORRST is an internally generated power-on reset pulse.
Figure 13-2. Power-On Reset Recovery 13.2.3.2 Computer Operating Properly (COP) Reset A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP bit in the system integration module (SIM) reset status register. To clear the COP counter and prevent a COP reset, write any value to the COP control register at location $FFFF.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 136 Freescale Semiconductor
Resets
13.2.3.3 Low-Voltage Inhibit Reset A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the LVITRIPF voltage. An LVI reset: * Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096 CGMXCLK cycles after the power supply voltage rises to the LVITRIPR voltage * Drives the RST pin low for as long as VDD is below the LVITRIPR voltage and during the oscillator stabilization delay * Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay * Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay * Sets the LVI bit in the SIM reset status register 13.2.3.4 Illegal Opcode Reset An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal opcode reset sets the ILOP bit in the SIM reset status register. If the stop enable bit, STOP, in the CONFIG1 register is a 0, the STOP instruction causes an illegal opcode reset. 13.2.3.5 Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal address reset sets the ILAD bit in the SIM reset status register. A data fetch from an unmapped address does not generate a reset.
13.2.4 SIM Reset Status Register
This read-only register contains flags to show reset sources. All flag bits are automatically cleared following a read of the register. Reset service can read the SIM reset status register to clear the register after power-on reset and to determine the source of any subsequent reset. The register is initialized on power-up as shown with the POR bit set and all other bits cleared. During a POR or any other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32 CGMXCLK cycles later. If the pin is not above a VIH at that time, then the PIN bit in the SRSR may be set in addition to whatever other bits are set. NOTE Only a read of the SIM reset status register clears all reset flags. After multiple resets from different sources without reading the register, multiple flags remain set.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 137
Resets and Interrupts Address: Read: Write: POR: 1 0 0 0 0 0 0 0 = Unimplemented $FE01 Bit 7 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 MODRST 1 LVI Bit 0 0
Figure 13-3. SIM Reset Status Register (SRSR) POR -- Power-On Reset Flag 1 = Power-on reset since last read of SRSR 0 = Read of SRSR since last power-on reset PIN -- External Reset Flag 1 = External reset via RST pin since last read of SRSR 0 = POR or read of SRSR since last external reset COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by timeout of COP counter 0 = POR or read of SRSR since any reset ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR since any reset ILAD -- Illegal Address Reset Bit 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR since any reset MODRST -- Monitor Mode Entry Module Reset Bit 1 = Last reset caused by forced monitor mode entry. 0 = POR or read of SRSR since any reset LVI -- Low-Voltage Inhibit Reset Bit 1 = Last reset caused by low-power supply voltage 0 = POR or read of SRSR since any reset
13.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An interrupt does not stop the operation of the instruction being executed, but begins when the current instruction completes its operation.
13.3.1 Effects
An interrupt: * Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the CPU registers from the stack so that normal processing can resume. * Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other interrupt can take precedence, regardless of its priority. * Loads the program counter with a user-defined vector address
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 138 Freescale Semiconductor
Interrupts
* * *
5 4 STACKING ORDER 3 2 1
CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER (LOW BYTE)(1) PROGRAM COUNTER (HIGH BYTE) PROGRAM COUNTER (LOW BYTE)
1 2 3 4 5 UNSTACKING ORDER
* * *
$00FF DEFAULT ADDRESS ON RESET 1. High byte of index register is not stacked.
Figure 13-4. Interrupt Stacking Order After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the example shown in Figure 13-5, if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 13-5. Interrupt Recognition Example
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 139
Resets and Interrupts
FROM RESET
BREAK INTERRUPT ? NO YES
YES
BIT SET? IIBIT SET? NO IRQ INTERRUPT ? NO ICG INTERRUPT ? NO YES
YES
OTHER INTERRUPTS ? NO
YES
STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION ? NO RTI INSTRUCTION ? NO
YES
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 13-6. Interrupt Processing The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 140 Freescale Semiconductor
Interrupts
modifies the H register or uses the indexed addressing mode, save the H register and then restore it prior to exiting the routine.
13.3.2 Sources
The sources in Table 13-1 can generate CPU interrupt requests. 13.3.2.1 Software Interrupt (SWI) Instruction The software interrupt instruction (SWI) causes a non-maskable interrupt. NOTE A software interrupt pushes PC onto the stack. An SWI does not push PC - 1, as a hardware interrupt does. Table 13-1. Interrupt Sources
Source Reset SWI instruction IRQ pin ICG clock monitor TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 channel 1 TIM2 overflow SPI receiver full SPI overflow SPI mode fault SPI transmitter empty SCI receiver overrun SCI noise fag SCI framing error SCI parity error SCI receiver full SCI input idle SCI transmitter empty SCI transmission complete Keyboard pin ADC conversion complete Timebase Flag None None IRQF CMF CH0F CH1F TOF CH0F CH1F TOF SPRF OVRF MODF SPTE OR NF FE PE SCRF IDLE SCTE TC KEYF COCO TBIF Mask(1) None None IMASK1 CMIE CH0IE CH1IE TOIE CH0IE CH1IE TOIE SPRIE ERRIE ERRIE SPTIE ORIE NEIE FEIE PEIE SCRIE ILIE SCTIE TCIE IMASKK AIEN TBIE IF12 IF13 IF14 IF15 IF16 12 13 14 15 16 $FFE4-$FFE5 $FFE2-$FFE3 $FFE0-$FFE1 $FFDE-$FFDF $FFDC-$FFDD IF11 11 $FFE6-$FFE7 IF10 10 $FFE8-$FFE9 IF9 9 $FFEA-$FFEB INT Register Flag None None IF1 IF2 IF3 IF4 IF5 IF6 IF7 IF8 Priority(2) 0 0 1 2 3 4 5 6 7 8 Vector Address $FFFE-$FFFF $FFFC-$FFFD $FFFA-$FFFB $FFF8-$FFF9 $FFF6-$FFF7 $FFF4-$FFF5 $FFF2-$FFF3 $FFF0-$FFF1 $FFEE-$FFEF $FFEC-$FFED
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. 2. 0 = highest priority
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 141
Resets and Interrupts
13.3.2.2 Break Interrupt The break module causes the CPU to execute an SWI instruction at a software-programmable break point. 13.3.2.3 IRQ Pin A logic 0 on the IRQ1 pin latches an external interrupt request. 13.3.2.4 Internal Clock Generator (ICG) The ICG can generate a CPU interrupt request every time the selected internal or external clock becomes inactive. When the clock monitor CMON bit is set and the currently selected clock becomes inactive, the clock monitor interrupt flag CMF is set. The clock monitor interrupt enable bit (CMIE) enables ICG CPU interrupt requests. CMIE, CMF, and CMON are in the ICGCR control register. 13.3.2.5 Timer Interface Module 1 (TIM1) TIM1 CPU interrupt sources: * TIM1 overflow flag (TOF) -- The TOF bit is set when the TIM1 counter value rolls over to $0000 after matching the value in the TIM1 counter modulo registers. The TIM1 overflow interrupt enable bit, TOIE, enables TIM1 overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status and control register. * TIM1 channel flags (CH1F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM1 CPU interrupt requests. CHxF and CHxIE are in the TIM1 channel x status and control register. 13.3.2.6 Timer Interface Module 2 (TIM2) TIM2 CPU interrupt sources: * TIM2 overflow flag (TOF) -- The TOF bit is set when the TIM2 counter value rolls over to $0000 after matching the value in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable bit, TOIE, enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status and control register. * TIM2 channel flags (CH1F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM2 CPU interrupt requests. CHxF and CHxIE are in the TIM2 channel x status and control register. 13.3.2.7 Serial Peripheral Interface (SPI) SPI CPU interrupt sources: * SPI receiver full bit (SPRF) -- The SPRF bit is set every time a byte transfers from the shift register to the receive data register. The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU interrupt requests. SPRF is in the SPI status and control register and SPRIE is in the SPI control register. * SPI transmitter empty (SPTE) -- The SPTE bit is set every time a byte transfers from the transmit data register to the shift register. The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control register.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 142 Freescale Semiconductor
Interrupts
*
*
Mode fault bit (MODF) -- The MODF bit is set in a slave SPI if the SS pin goes high during a transmission with the mode fault enable bit (MODFEN) set. In a master SPI, the MODF bit is set if the SS pin goes low at any time with the MODFEN bit set. The error interrupt enable bit, ERRIE, enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and control register. Overflow bit (OVRF) -- The OVRF bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE, enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control register.
13.3.2.8 Serial Communications Interface (SCI) SCI CPU interrupt sources: * SCI transmitter empty bit (SCTE) -- SCTE is set when the SCI data register transfers a character to the transmit shift register. The SCI transmit interrupt enable bit, SCTIE, enables transmitter CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is in SCI control register 2. * Transmission complete bit (TC) -- TC is set when the transmit shift register and the SCI data register are empty and no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, enables transmitter CPU interrupt requests. TC is in SCI status register 1. TCIE is in SCI control register 2. * SCI receiver full bit (SCRF) -- SCRF is set when the receive shift register transfers a character to the SCI data register. The SCI receive interrupt enable bit, SCRIE, enables receiver CPU interrupts. SCRF is in SCI status register 1. SCRIE is in SCI control register 2. * Idle input bit (IDLE) -- IDLE is set when 10 or 11 consecutive 1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE, enables IDLE CPU interrupt requests. IDLE is in SCI status register 1. ILIE is in SCI control register 2. * Receiver overrun bit (OR) -- OR is set when the receive shift register shifts in a new character before the previous character was read from the SCI data register. The overrun interrupt enable bit, ORIE, enables OR to generate SCI error CPU interrupt requests. OR is in SCI status register 1. ORIE is in SCI control register 3. * Noise flag (NF) -- NF is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, enables NF to generate SCI error CPU interrupt requests. NF is in SCI status register 1. NEIE is in SCI control register 3. * Framing error bit (FE) -- FE is set when a 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, enables FE to generate SCI error CPU interrupt requests. FE is in SCI status register 1. FEIE is in SCI control register 3. * Parity error bit (PE) -- PE is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, enables PE to generate SCI error CPU interrupt requests. PE is in SCI status register 1. PEIE is in SCI control register 3. 13.3.2.9 KBD0-KBD7 Pins A logic 0 on a keyboard interrupt pin latches an external interrupt request. 13.3.2.10 Analog-to-Digital Converter (ADC) When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 143
Resets and Interrupts
13.3.2.11 Timebase Module (TBM) The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2-TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing a 1 to the TACK bit.
13.3.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 13-2 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 13-2. Interrupt Source Flags
Interrupt Source Reset SWI instruction IRQ pin ICG clock monitor TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 channel 1 TIM2 overflow SPI receive SPI transmit SCI error SCI receive SCI transmit Keyboard ADC conversion complete Timebase Interrupt Status Register Flag -- -- IF1 IF2 IF3 IF4 IF5 IF6 IF7 IF8 IF9 IF10 IF11 IF12 IF13 IF14 IF15 IF16
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 144 Freescale Semiconductor
Interrupts
13.3.3.1 Interrupt Status Register 1
Address: Read: Write: Reset: $FE04 Bit 7 IF6 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 IF2 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 13-7. Interrupt Status Register 1 (INT1) IF6-IF1 -- Interrupt Flags 6-1 These flags indicate the presence of interrupt requests from the sources shown in Table 13-2. 1 = Interrupt request present 0 = No interrupt request present Bit 1 and Bit 0 -- Always read 0 13.3.3.2 Interrupt Status Register 2
Address: Read: Write: Reset: $FE05 Bit 7 IF14 R 0 R 6 IF13 R 0 = Reserved 5 IF12 R 0 4 IF11 R 0 3 IF10 R 0 2 IF9 R 0 1 IF8 R 0 Bit 0 IF7 R 0
Figure 13-8. Interrupt Status Register 2 (INT2) IF14-IF7 -- Interrupt Flags 14-7 These flags indicate the presence of interrupt requests from the sources shown in Table 13-2. 1 = Interrupt request present 0 = No interrupt request present 13.3.3.3 Interrupt Status Register 3
Address: Read: Write: Reset: $FE06 Bit 7 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 IF16 R 0 Bit 0 IF15 R 0
Figure 13-9. Interrupt Status Register 3 (INT3) IF16-IF15 -- Interrupt Flags 16-15 This flag indicates the presence of an interrupt request from the source shown in Table 13-2. 1 = Interrupt request present 0 = No interrupt request present Bits 7-2 -- Always read 0
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 145
Resets and Interrupts
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 146 Freescale Semiconductor
Chapter 14 Enhanced Serial Communications Interface (ESCI) Module
14.1 Introduction
The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU).
14.2 Features
Features include: * Full-duplex operation * Standard mark/space non-return-to-zero (NRZ) format * Programmable baud rates * Programmable 8-bit or 9-bit character length * Separately enabled transmitter and receiver * Separate receiver and transmitter central processor unit (CPU) interrupt requests * Programmable transmitter output polarity * Two receiver wakeup methods: - Idle line wakeup - address mark wakeup * Interrupt-driven operation with eight interrupt flags: - Transmitter empty - Transmission complete - Receiver full - Idle receiver input - Receiver overrun - Noise error - Framing error - Parity error * Receiver framing error detection * Hardware parity checking * 1/16 bit-time noise detection
14.3 Pin Name Conventions
The generic names of the ESCI input/output (I/O) pins are: * RxD (receive data) * TxD (transmit data) ESCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an ESCI input or output reflects the name of the shared port pin. Table 14-1 shows the full names and the generic names of the ESCI I/O pins. The generic pin names appear in the text of this section.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 147
Enhanced Serial Communications Interface (ESCI) Module
INTERNAL BUS PORTA M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(3) SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA SERIAL PERIPHERAL INTERFACE MODULE PORTB DDRB PTA7/KBD7- PTA0/KBD0(1) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1)(2) PTC3(1)(2) PTC2(1)(2) PTC1(1)(2) PTC0(1)(2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE2 PTE1/RxD PTE0/TxD
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH MC68HC908GT16 -- 15,872 BYTES MC68HC908GT8 -- 7,680 BYTES USER RAM -- 512 BYTES MONITOR ROM -- 304 BYTES FLASH PROGRAMMING ROUTINES ROM -- 720 BYTES USER FLASH VECTOR SPACE -- 36 BYTES
PTE4/OSC1 PTE3/OSC2
INTERNAL CLOCK GENERATOR MODULE
IRQ(3) VREFH VREFL
MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE
PORTE
MONITOR MODULE DDRE
PORTD
DDRD
PORTC
DDRC
SECURITY MODULE
POWER
MONITOR MODE ENTRY MODULE
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
Figure 14-1. Block Diagram Highlighting ESCI Block and Pins Table 14-1. Pin Name Conventions
Generic Pin Names Full Pin Names RxD PTE1/RxD TxD PTE0/TxD
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 148 Freescale Semiconductor
Functional Description
14.4 Functional Description
Figure 14-2 shows the structure of the ESCI module. The ESCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the ESCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the ESCI, writes the data to be transmitted, and processes received data. For reference, a summary of the ESCI module input/output registers is provided in Figure 14-4.
INTERNAL BUS
TRANSMITTER INTERRUPT CONTROL
ESCI DATA REGISTER RECEIVE SHIFT REGISTER LINR SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCTE TC SCRF IDLE
ESCI DATA REGISTER RECEIVER INTERRUPT CONTROL ERROR INTERRUPT CONTROL TRANSMIT SHIFT REGISTER TXINV R8 T8
RxD ARBITERSCI_TxD TxD
RxD
OR NF FE PE LOOPS LOOPS ENSCI FLAG CONTROL BKF RPF BAUD RATE GENERATOR M WAKE ILTY PEN PTY DATA SELECTION CONTROL
ORIE NEIE FEIE PEIE
WAKEUP CONTROL
RECEIVE CONTROL
TRANSMIT CONTROL
ENSCI
LINT
PRESCALER BUS CLOCK
/4
PRESCALER
/ 16
Figure 14-2. ESCI Module Block Diagram
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 149
Enhanced Serial Communications Interface (ESCI) Module
14.4.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 14-3.
PARITY OR DATA BIT BIT 7 STOP BIT PARITY OR DATA BIT BIT 6 BIT 7 BIT 8
START BIT
8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
NEXT START BIT
START BIT
9-BIT DATA FORMAT (BIT M IN SCC1 SET) BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
NEXT START BIT STOP BIT
Figure 14-3. SCI Data Formats
Addr. $0009 Register Name ESCI Prescaler Register Read: (SCPSC) Write: See page 170. Reset: ESCI Arbiter Control Read: Register (SCIACTL) Write: See page 174. Reset: ESCI Arbiter Data Read: Register (SCIADAT) Write: See page 175. Reset: ESCI Control Register 1 Read: (SCC1) Write: See page 161. Reset: ESCI Control Register 2 Read: (SCC2) Write: See page 163. Reset: ESCI Control Register 3 Read: (SCC3) Write: See page 165. Reset: ESCI Status Register 1 Read: (SCS1) Write: See page 166. Reset: ESCI Status Register 2 Read: (SCS2) Write: See page 168. Reset: ESCI Data Register Read: (SCDR) Write: See page 169. Reset: ESCI Baud Rate Register Read: (SCBR) Write: See page 169. Reset: Bit 7 PDS2 0 AM1 0 ARD7 0 LOOPS 0 SCTIE 0 R8 U SCTE 1 0 0 R7 T7 6 PDS1 0 ALOST 0 ARD6 0 ENSCI 0 TCIE 0 T8 0 TC 1 0 0 R6 T6 5 PDS0 0 AM0 0 ARD5 0 TXINV 0 SCRIE 0 R 0 SCRF 0 0 0 R5 T5 4 PSSB4 0 ACLK 0 ARD4 0 M 0 ILIE 0 R 0 IDLE 0 0 3 PSSB3 0 AFIN 0 ARD3 0 WAKE 0 TE 0 ORIE 0 OR 0 0 2 PSSB2 0 ARUN 0 ARD2 0 ILTY 0 RE 0 NEIE 0 NF 0 0 0 R2 T2 1 PSSB1 0 AROVFL 0 ARD1 0 PEN 0 RWU 0 FEIE 0 FE 0 BKF 0 R1 T1 Bit 0 PSSB0 0 ARD8 0 ARD0 0 PTY 0 SBK 0 PEIE 0 PE 0 RPF 0 R0 T0
$000A
$000B
$0013
$0014
$0015
$0016
$0017
$0018
0 0 R4 R3 T4 T3 Unaffected by reset SCP0 0 R R 0 = Reserved
$0019
R 0
LINR
SCP1
SCR2
SCR1
SCR0 0
0 0 = Unimplemented
0 0 U = Unaffected
Figure 14-4. ESCI I/O Register Summary
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 150 Freescale Semiconductor
Functional Description
14.4.2 Transmitter
Figure 14-5 shows the structure of the SCI transmitter and the registers are summarized in Figure 14-4.
INTERNAL BUS
/4
SCP1 SCP0 SCR1 SCR2 SCR0 TRANSMITTER CPU INTERRUPT REQUEST
PRESCALER
BAUD DIVIDER
/ 16
ESCI DATA REGISTER
H
8
7
6
5
4
3
2
1
0
START L
STOP
11-BIT TRANSMIT SHIFT REGISTER
SCI_TxD
TXINV
PRESCALER
M PEN PTY PARITY GENERATION LOAD FROM SCDR
BUS CLOCK
SHIFT ENABLE
PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0
T8
TRANSMITTER CONTROL LOGIC
SCTE SCTE SCTIE TC TCIE
PREAMBLE (ALL ONES)
LOOPS SCTIE TC TCIE ENSCI TE LINT
Figure 14-5. ESCI Transmitter 14.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). 14.4.2.2 Character Transmission During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin. The ESCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 151
BREAK (ALL ZEROS) SBK
PDS2
MSB
Enhanced Serial Communications Interface (ESCI) Module
To initiate an ESCI transmission: 1. Enable the ESCI by writing a 1 to the enable ESCI bit (ENSCI) in ESCI control register 1 (SCC1). 2. Enable the transmitter by writing a 1 to the transmitter enable bit (TE) in ESCI control register 2 (SCC2). 3. Clear the ESCI transmitter empty bit (SCTE) by first reading ESCI status register 1 (SCS1) and then writing to the SCDR. For 9-bit data, also write the T8 bit in SCC3. 4. Repeat step 3 for each subsequent transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A 0 start bit automatically goes into the least significant bit (LSB) position of the transmit shift register. A 1 stop bit goes into the most significant bit (MSB) position. The ESCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the ESCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in ESCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins. 14.4.2.3 Break Characters Writing a 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. For TXINV = 0 (output not inverted), a transmitted break character contains all 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1 and the LINR bits in SCBR. As long as SBK is at 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one 1. The automatic 1 at the end of a break character guarantees the recognition of the start bit of the next character. When LINR is cleared in SCBR, the ESCI recognizes a break character when a start bit is followed by eight or nine 0 data bits and a 0 where the stop bit should be, resulting in a total of 10 or 11 consecutive 0 data bits. When LINR is set in SCBR, the ESCI recognizes a break character when a start bit is followed by 9 or 10 0 data bits and a 0 where the stop bit should be, resulting in a total of 11 or 12 consecutive 0 data bits. Receiving a break character has these effects on ESCI registers: * Sets the framing error bit (FE) in SCS1 * Sets the ESCI receiver full bit (SCRF) in SCS1 * Clears the ESCI data register (SCDR) * Clears the R8 bit in SCC3 * Sets the break flag bit (BKF) in SCS2 * May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits 14.4.2.4 Idle Characters For TXINV = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 152 Freescale Semiconductor
Functional Description
If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted. NOTE When queueing an idle character, return the TE bit to 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. A good time to toggle the TE bit for a queued idle character is when the SCTE bit becomes set and just before writing the next byte to the SCDR. 14.4.2.5 Inversion of Transmitted Output The transmit inversion bit (TXINV) in ESCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values including idle, break, start, and stop bits, are inverted when TXINV is at 1. See 14.8.1 ESCI Control Register 1. 14.4.2.6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the ESCI transmitter: * ESCI transmitter empty (SCTE) -- The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the ESCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. * Transmission complete (TC) -- The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests.
14.4.3 Receiver
Figure 14-6 shows the structure of the ESCI receiver. The receiver I/O registers are summarized in Figure 14-4. 14.4.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 14.4.3.2 Character Reception During an ESCI reception, the receive shift register shifts characters in from the RxD pin. The ESCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The ESCI receiver full bit, SCRF, in ESCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the ESCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 153
Enhanced Serial Communications Interface (ESCI) Module
INTERNAL BUS
LINR SCP1 SCP0
SCR1 SCR2 SCR0 START 0 L RWU PRESCALER BAUD DIVIDER ESCI DATA REGISTER
STOP
/4
PRESCALER
/ 16
DATA RECOVERY
11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1
RxD
H ALL ONES
BUS CLOCK
BKF PDS2 PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0 M WAKE ILTY PEN PTY RPF
ALL ZEROS
MSB
SCRF WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE IDLE
R8
ILIE
CPU INTERRUPT REQUEST
SCRIE
OR ORIE ERROR CPU INTERRUPT REQUEST NF NEIE FE FEIE PE PEIE
OR ORIE NF NEIE FE FEIE PE PEIE
Figure 14-6. ESCI Receiver Block Diagram
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 154 Freescale Semiconductor
Functional Description
14.4.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at these times (see Figure 14-7): * After every start bit * After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid 0) To locate the start bit, data recovery logic does an asynchronous search for a 0 preceded by three 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
START BIT LSB
RxD
SAMPLES
START BIT QUALIFICATION
START BIT DATA VERIFICATION SAMPLING
RT CLOCK RT CLOCK STATE RT CLOCK RESET RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4
Figure 14-7. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 14-2 summarizes the results of the start bit verification samples. Table 14-2. Start Bit Verification
RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-3 summarizes the results of the data bit samples.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 155
Enhanced Serial Communications Interface (ESCI) Module
Table 14-3. Data Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0
NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-4 summarizes the results of the stop bit samples. Table 14-4. Stop Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0
14.4.3.4 Framing Errors If the data recovery logic does not detect a 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. 14.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 156 Freescale Semiconductor
Functional Description
Slow Data Tolerance Figure 14-8 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
MSB STOP
RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT15 RT16 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
DATA SAMPLES
Figure 14-8. Slow Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 14-8, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is:
154 - 147 ------------------------- x 100 = 4.54% 154
For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 14-8, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is:
170 - 163 ------------------------- x 100 = 4.12% 170
Fast Data Tolerance Figure 14-9 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10.
STOP IDLE OR NEXT CHARACTER
RECEIVER RT CLOCK RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14
DATA SAMPLE
Figure 14-9. Fast Data
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 157
Enhanced Serial Communications Interface (ESCI) Module
For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 14-9, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is
154 - 160 ------------------------- x 100 = 3.90%. 154
For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 14-9, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is:
170 - 176 ------------------------- x 100 = 3.53%. 170
14.4.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: 1. Address mark -- An address mark is a 1 in the MSB position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the ESCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. 2. Idle input line condition -- When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the ESCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. NOTE With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle will cause the receiver to wake up.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 158 Freescale Semiconductor
Low-Power Modes
14.4.3.7 Receiver Interrupts These sources can generate CPU interrupt requests from the ESCI receiver: * ESCI receiver full (SCRF) -- The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting the ESCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. * Idle input (IDLE) -- The IDLE bit in SCS1 indicates that 10 or 11 consecutive 1s shifted in from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU interrupt requests. 14.4.3.8 Error Interrupts These receiver error flags in SCS1 can generate CPU interrupt requests: * Receiver overrun (OR) -- The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The previous character remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate ESCI error CPU interrupt requests. * Noise flag (NF) -- The NF bit is set when the ESCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate ESCI error CPU interrupt requests. * Framing error (FE) -- The FE bit in SCS1 is set when a 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate ESCI error CPU interrupt requests. * Parity error (PE) -- The PE bit in SCS1 is set when the ESCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate ESCI error CPU interrupt requests.
14.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
14.5.1 Wait Mode
The ESCI module remains active in wait mode. Any enabled CPU interrupt request from the ESCI module can bring the MCU out of wait mode. If ESCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction.
14.5.2 Stop Mode
The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states. ESCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission or reception results in invalid data.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 159
Enhanced Serial Communications Interface (ESCI) Module
14.6 ESCI During Break Module Interrupts
The BCFE bit in the break flag control register (SBFCR) enables software to clear status bits during the break state. See Chapter 19 Development Support. To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the second step clears the status bit.
14.7 I/O Signals
Port E shares two of its pins with the ESCI module. The two ESCI I/O pins are: * PTE0/TxD -- transmit data * PTE1/RxD -- receive data
14.7.1 PTE0/TxD (Transmit Data)
The PTE0/TxD pin is the serial data output from the ESCI transmitter. The ESCI shares the PTE0/TxD pin with port E. When the ESCI is enabled, the PTE0/TxD pin is an output regardless of the state of the DDRE0 bit in data direction register E (DDRE).
14.7.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the ESCI receiver. The ESCI shares the PTE1/RxD pin with port E. When the ESCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE).
14.8 I/O Registers
These I/O registers control and monitor ESCI operation: * ESCI control register 1, SCC1 * ESCI control register 2, SCC2 * ESCI control register 3, SCC3 * ESCI status register 1, SCS1 * ESCI status register 2, SCS2 * ESCI data register, SCDR * ESCI baud rate register, SCBR * ESCI prescaler register, SCPSC * ESCI arbiter control register, SCIACTL * ESCI arbiter data register, SCIADAT
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 160 Freescale Semiconductor
I/O Registers
14.8.1 ESCI Control Register 1
ESCI control register 1 (SCC1): * Enables loop mode operation * Enables the ESCI * Controls output polarity * Controls character length * Controls ESCI wakeup method * Controls idle character detection * Enables parity function * Controls parity type
Address: $0013 Bit 7 Read: Write: Reset: LOOPS 0 6 ENSCI 0 5 TXINV 0 4 M 0 3 WAKE 0 2 ILTY 0 1 PEN 0 Bit 0 PTY 0
Figure 14-10. ESCI Control Register 1 (SCC1) LOOPS -- Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the ESCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI -- Enable ESCI Bit This read/write bit enables the ESCI and the ESCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in ESCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = ESCI enabled 0 = ESCI disabled TXINV -- Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted NOTE Setting the TXINV bit inverts all transmitted values including idle, break, start, and stop bits. M -- Mode (Character Length) Bit This read/write bit determines whether ESCI characters are eight or nine bits long (See Table 14-5).The ninth bit can serve as a receiver wakeup signal or as a parity bit. Reset clears the M bit. 1 = 9-bit ESCI characters 0 = 8-bit ESCI characters
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 161
Enhanced Serial Communications Interface (ESCI) Module
WAKE -- Wakeup Condition Bit This read/write bit determines which condition wakes up the ESCI: a 1 (address mark) in the MSB position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup Table 14-5. Character Format Selection
Control Bits M 0 1 0 0 1 1 PEN:PTY 0X 0X 10 11 10 11 Start Bits 1 1 1 1 1 1 Data Bits 8 9 7 7 8 8 Character Format Parity None None Even Odd Even Odd Stop Bits 1 1 1 1 1 1 Character Length 10 bits 11 bits 10 bits 10 bits 11 bits 11 bits
ILTY -- Idle Line Type Bit This read/write bit determines when the ESCI starts counting 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN -- Parity Enable Bit This read/write bit enables the ESCI parity function (see Table 14-5). When enabled, the parity function inserts a parity bit in the MSB position (see Table 14-3). Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled PTY -- Parity Bit This read/write bit determines whether the ESCI generates and checks for odd parity or even parity (see Table 14-5). Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE Changing the PTY bit in the middle of a transmission or reception can generate a parity error.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 162 Freescale Semiconductor
I/O Registers
14.8.2 ESCI Control Register 2
ESCI control register 2 (SCC2): * Enables these CPU interrupt requests: - SCTE bit to generate transmitter CPU interrupt requests - TC bit to generate transmitter CPU interrupt requests - SCRF bit to generate receiver CPU interrupt requests - IDLE bit to generate receiver CPU interrupt requests * Enables the transmitter * Enables the receiver * Enables ESCI wakeup * Transmits ESCI break characters
Address: $0014 Bit 7 Read: Write: Reset: SCTIE 0 6 TCIE 0 5 SCRIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0
Figure 14-11. ESCI Control Register 2 (SCC2) SCTIE -- ESCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate ESCI transmitter CPU interrupt requests. Setting the SCTIE bit in SCC2 enables the SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE -- Transmission Complete Interrupt Enable Bit : This read/write bit enables the TC bit to generate ESCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests SCRIE -- ESCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate ESCI receiver CPU interrupt requests. Setting the SCRIE bit in SCC2 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE -- Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate ESCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 163
Enhanced Serial Communications Interface (ESCI) Module
TE -- Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition (1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled NOTE Writing to the TE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1. RE -- Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE Writing to the RE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1. RWU -- Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK -- Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a 1. The 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted NOTE Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the ESCI to send a break character instead of a preamble.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 164 Freescale Semiconductor
I/O Registers
14.8.3 ESCI Control Register 3
ESCI control register 3 (SCC3): * Stores the ninth ESCI data bit received and the ninth ESCI data bit to be transmitted. * Enables these interrupts: - Receiver overrun - Noise error - Framing error - Parity error
Address: Read: Write: Reset: $0015 Bit 7 R8 U 6 T8 5 R 4 R 0 R 3 ORIE 0 = Reserved 2 NEIE 1 FEIE Bit 0 PEIE 0
0 0 = Unimplemented
0 0 U = Unaffected
Figure 14-12. ESCI Control Register 3 (SCC3) R8 -- Received Bit 8 When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the ESCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 -- Transmitted Bit 8 When the ESCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset clears the T8 bit. ORIE -- Receiver Overrun Interrupt Enable Bit This read/write bit enables ESCI error CPU interrupt requests generated by the receiver overrun bit, OR. Reset clears ORIE. 1 = ESCI error CPU interrupt requests from OR bit enabled 0 = ESCI error CPU interrupt requests from OR bit disabled NEIE -- Receiver Noise Error Interrupt Enable Bit This read/write bit enables ESCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = ESCI error CPU interrupt requests from NE bit enabled 0 = ESCI error CPU interrupt requests from NE bit disabled FEIE -- Receiver Framing Error Interrupt Enable Bit This read/write bit enables ESCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = ESCI error CPU interrupt requests from FE bit enabled 0 = ESCI error CPU interrupt requests from FE bit disabled PEIE -- Receiver Parity Error Interrupt Enable Bit This read/write bit enables ESCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE. 1 = ESCI error CPU interrupt requests from PE bit enabled 0 = ESCI error CPU interrupt requests from PE bit disabled
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 165
Enhanced Serial Communications Interface (ESCI) Module
14.8.4 ESCI Status Register 1
ESCI status register 1 (SCS1) contains flags to signal these conditions: * Transfer of SCDR data to transmit shift register complete * Transmission complete * Transfer of receive shift register data to SCDR complete * Receiver input idle * Receiver overrun * Noisy data * Framing error * Parity error
Address: Read: Write: Reset: 1 1 0 0 0 0 0 0 = Unimplemented $0016 Bit 7 SCTE 6 TC 5 SCRF 4 IDLE 3 OR 2 NF 1 FE Bit 0 PE
Figure 14-13. ESCI Status Register 1 (SCS1) SCTE -- ESCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an ESCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an ESCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC -- Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an ESCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is cleared automatically when data, preamble, or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF -- ESCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the ESCI data register. SCRF can generate an ESCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set the SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE -- Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. IDLE generates an ESCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 166 Freescale Semiconductor
I/O Registers
a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) OR -- Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an ESCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 14-14 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register.
NORMAL FLAG CLEARING SEQUENCE SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = 1 OR = 1 READ SCDR BYTE 3 SCRF = 0 OR = 0
BYTE 1 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 2
BYTE 3
DELAYED FLAG CLEARING SEQUENCE SCRF = 1 OR = 1 SCRF = 1 SCRF = 0 OR = 1 SCRF = 1 OR = 1 BYTE 3
BYTE 1
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1
Figure 14-14. Flag Clearing Sequence
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 167
Enhanced Serial Communications Interface (ESCI) Module
NF -- Receiver Noise Flag Bit This clearable, read-only bit is set when the ESCI detects noise on the RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE -- Receiver Framing Error Bit This clearable, read-only bit is set when a 0 is accepted as the stop bit. FE generates an ESCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected PE -- Receiver Parity Error Bit This clearable, read-only bit is set when the ESCI detects a parity error in incoming data. PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected
14.8.5 ESCI Status Register 2
ESCI status register 2 (SCS2) contains flags to signal these conditions: * Break character detected * Incoming data
Address: Read: Write: Reset: $0017 Bit 7 0 0 6 0 5 0 4 0 0 3 0 0 2 0 0 1 BKF 0 Bit 0 RPF 0
0 0 = Unimplemented
Figure 14-15. ESCI Status Register 2 (SCS2) BKF -- Break Flag Bit This clearable, read-only bit is set when the ESCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected RPF -- Reception in Progress Flag Bit This read-only bit is set when the receiver detects a 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. Polling RPF before disabling the ESCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 168 Freescale Semiconductor
I/O Registers
14.8.6 ESCI Data Register
The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the ESCI data register.
Address: Read: Write: Reset: $0018 Bit 7 R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0
Unaffected by reset
Figure 14-16. ESCI Data Register (SCDR) R7/T7:R0/T0 -- Receive/Transmit Data Bits Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register. NOTE Do not use read-modify-write instructions on the ESCI data register.
14.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for both the receiver and the transmitter. NOTE There are two prescalers available to adjust the baud rate. One in the ESCI baud rate register and one in the ESCI prescaler register.
Address: Read: Write: Reset: $0019 Bit 7 R 0 6 LINR 0 5 SCP1 0 4 SCP0 0 R 3 R 0 = Reserved 2 SCR2 0 1 SCR1 0 Bit 0 SCR0 0
= Unimplemented
Figure 14-17. ESCI Baud Rate Register (SCBR) LINR -- LIN Receiver Bits This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol as shown in Table 14-6. Reset clears LINR. Table 14-6. ESCI LIN Control Bits
LINR 0 1 1 M X 0 1 Normal ESCI functionality 11-bit break detect enabled for LIN receiver 12-bit break detect enabled for LIN receiver Functionality
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 169
Enhanced Serial Communications Interface (ESCI) Module
SCP1 and SCP0 -- ESCI Baud Rate Register Prescaler Bits These read/write bits select the baud rate register prescaler divisor as shown in Table 14-7. Reset clears SCP1 and SCP0. Table 14-7. ESCI Baud Rate Prescaling
SCP[1:0] 00 01 10 11 Baud Rate Register Prescaler Divisor (BPD) 1 3 4 13
SCR2-SCR0 -- ESCI Baud Rate Select Bits These read/write bits select the ESCI baud rate divisor as shown in Table 14-8. Reset clears SCR2-SCR0. Table 14-8. ESCI Baud Rate Selection
SCR[2:1:0] 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128
14.8.8 ESCI Prescaler Register
The ESCI prescaler register (SCPSC) together with the ESCI baud rate register selects the baud rate for both the receiver and the transmitter. NOTE There are two prescalers available to adjust the baud rate. One in the ESCI baud rate register and one in the ESCI prescaler register.
Address: Read: Write: Reset: $0009 Bit 7 PDS2 0 6 PDS1 0 5 PDS0 0 4 PSSB4 0 3 PSSB3 0 2 PSSB2 0 1 PSSB1 0 Bit 0 PSSB0 0
Figure 14-18. ESCI Prescaler Register (SCPSC)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 170 Freescale Semiconductor
I/O Registers
PDS2-PDS0 -- Prescaler Divisor Select Bits These read/write bits select the prescaler divisor as shown in Table 14-9. Reset clears PDS2-PDS0. NOTE The setting of `000' will bypass this prescaler. It is not recommended to bypass the prescaler while ENSCI is set, because the switching is not glitch free. Table 14-9. ESCI Prescaler Division Ratio
PS[2:1:0] 000 001 010 011 100 101 110 111 Prescaler Divisor (PD) Bypass this prescaler 2 3 4 5 6 7 8
PSSB4-PSSB0 -- Clock Insertion Select Bits These read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve more timing resolution on the average prescaler frequency as shown in Table 14-10. Reset clears PSSB4-PSSB0. Table 14-10. ESCI Prescaler Divisor Fine Adjust
PSSB[4:3:2:1:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 Prescaler Divisor Fine Adjust (PDFA) 0/32 = 0 1/32 = 0.03125 2/32 = 0.0625 3/32 = 0.09375 4/32 = 0.125 5/32 = 0.15625 6/32 = 0.1875 7/32 = 0.21875 8/32 = 0.25 9/32 = 0.28125 10/32 = 0.3125 11/32 = 0.34375 12/32 = 0.375 13/32 = 0.40625 14/32 = 0.4375 Table continued on next page MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 171
Enhanced Serial Communications Interface (ESCI) Module
Table 14-10. ESCI Prescaler Divisor Fine Adjust (Continued)
PSSB[4:3:2:1:0] 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Prescaler Divisor Fine Adjust (PDFA) 15/32 = 0.46875 16/32 = 0.5 17/32 = 0.53125 18/32 = 0.5625 19/32 = 0.59375 20/32 = 0.625 21/32 = 0.65625 22/32 = 0.6875 23/32 = 0.71875 24/32 = 0.75 25/32 = 0.78125 26/32 = 0.8125 27/32 = 0.84375 28/32 = 0.875 29/32 = 0.90625 30/32 = 0.9375 31/32 = 0.96875
Use the following formula to calculate the ESCI baud rate: f Bus Baud rate = ----------------------------------------------------------------------------------64 x BPD x BD x ( PD + PDFA ) where: fBus = BPD = BD = PD = PDFA = Bus frequency Baud rate register prescaler divisor Baud rate divisor Prescaler divisor Prescaler divisor fine adjust
Table 14-11 shows the ESCI baud rates that can be generated with a 4.9152-MHz bus frequency.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 172 Freescale Semiconductor
I/O Registers
Table 14-11. ESCI Baud Rate Selection Examples
PS[2:1:0] 000 111 111 111 111 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 PSSB[4:3:2:1:0] XXXXX 00000 00001 00010 11111 XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX SCP[1:0] 00 00 00 00 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 Prescaler Divisor (BPD) 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 SCR[2:1:0] 000 000 000 000 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 1 1 1 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 Baud Rate (fBus= 4.9152 MHz) 76,800 9600 9562.65 9525.58 8563.07 38,400 19,200 9600 4800 2400 1200 600 25,600 12,800 6400 3200 1600 800 400 200 19,200 9600 4800 2400 1200 600 300 150 5908 2954 1477 739 369 185 92 46
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 173
Enhanced Serial Communications Interface (ESCI) Module
14.9 ESCI Arbiter
The ESCI module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time detection. The arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. The CPU can control operation mode via the ESCI arbiter control register (SCIACTL).
14.9.1 ESCI Arbiter Control Register
Address: Read: Write: Reset: $000A Bit 7 AM1 0 6 ALOST 0 5 AM0 0 4 ACLK 0 3 AFIN 0 2 ARUN 0 1 AROVFL 0 Bit 0 ARD8 0
= Unimplemented
Figure 14-19. ESCI Arbiter Control Register (SCIACTL) AM1 and AM0 -- Arbiter Mode Select Bits These read/write bits select the mode of the arbiter module as shown in Table 14-12. Reset clears AM1 and AM0. Table 14-12. ESCI Arbiter Selectable Modes
AM[1:0] 00 01 10 11 ESCI Arbiter Mode Idle / counter reset Bit time measurement Bus arbitration Reserved / do not use
ALOST -- Arbitration Lost Flag This read-only bit indicates loss of arbitration. Clear ALOST by writing a 0 to AM1. Reset clears ALOST. ACLK -- Arbiter Counter Clock Select Bit This read/write bit selects the arbiter counter clock source. Reset clears ACLK. 1 = Arbiter counter is clocked with one half of the ESCI input clock generated by the ESCI prescaler 0 = Arbiter counter is clocked with one half of the bus clock AFIN-- Arbiter Bit Time Measurement Finish Flag This read-only bit indicates bit time measurement has finished. Clear AFIN by writing any value to SCIACTL. Reset clears AFIN. 1 = Bit time measurement has finished 0 = Bit time measurement not yet finished ARUN-- Arbiter Counter Running Flag This read-only bit indicates the arbiter counter is running. Reset clears ARUN. 1 = Arbiter counter running 0 = Arbiter counter stopped
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 174 Freescale Semiconductor
ESCI Arbiter
AROVFL-- Arbiter Counter Overflow Bit This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to SCIACTL. Writing 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears AROVFL. 1 = Arbiter counter overflow has occurred 0 = No arbiter counter overflow has occurred ARD8-- Arbiter Counter MSB This read-only bit is the MSB of the 9-bit arbiter counter. Clear ARD8 by writing any value to SCIACTL. Reset clears ARD8.
14.9.2 ESCI Arbiter Data Register
Address: $000B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented ARD7 6 ARD6 5 ARD5 4 ARD4 3 ARD3 2 ARD2 1 ARD1 Bit 0 ARD0
Figure 14-20. ESCI Arbiter Data Register (SCIADAT) ARD7-ARD0 -- Arbiter Least Significant Counter Bits These read-only bits are the eight LSBs of the 9-bit arbiter counter. Clear ARD7-ARD0 by writing any value to SCIACTL. Writing 0s to AM1 and AM0 permanently resets the counter and keeps it in this idle state. Reset clears ARD7-ARD0.
14.9.3 Bit Time Measurement
Two bit time measurement modes, described here, are available according to the state of ACLK. 1. ACLK = 0 -- The counter is clocked with one half of the bus clock. The counter is started when a falling edge on the RxD pin is detected. The counter will be stopped on the next falling edge. ARUN is set while the counter is running, AFIN is set on the second falling edge on RxD (for instance, the counter is stopped). This mode is used to recover the received baud rate. See Figure 14-21. 2. ACLK = 1 -- The counter is clocked with one half of the ESCI input clock generated by the ESCI prescaler. The counter is started when a 0 is detected on RxD (see Figure 14-22). A 0 on RxD on enabling the bit time measurement with ACLK = 1 leads to immediate start of the counter (see Figure 14-23). The counter will be stopped on the next rising edge of RxD. This mode is used to measure the length of a received break.
14.9.4 Arbitration Mode
If AM[1:0] is set to 10, the arbiter module operates in arbitration mode. On every rising edge of SCI_TxD (output of the ESCI module, internal chip signal), the counter is started. When the counter reaches $38 (ACLK = 0) or $08 (ACLK = 1), RxD is statically sensed. If in this case, RxD is sensed low (for example, another bus is driving the bus dominant) ALOST is set. As long as ALOST is set, the TxD pin is forced to 1, resulting in a seized transmission. If SCI_TxD is sensed 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration operation will be restarted after the next rising edge of SCI_TxD.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 175
Enhanced Serial Communications Interface (ESCI) Module
MEASURED TIME RXD
COUNTER STARTS, ARUN = 1
COUNTER STOPS, AFIN = 1
Figure 14-21. Bit Time Measurement with ACLK = 0
CPU WRITES SCIACTL WITH $20
MEASURED TIME RXD
CPU WRITES SCIACTL WITH $30 COUNTER STARTS, ARUN = 1
COUNTER STOPS, AFIN = 1
Figure 14-22. Bit Time Measurement with ACLK = 1, Scenario A
MEASURED TIME RXD
CPU WRITES SCIACTL WITH $30
Figure 14-23. Bit Time Measurement with ACLK = 1, Scenario B
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 176 Freescale Semiconductor
CPU READS RESULT OUT OF SCIADAT
COUNTER STARTS, ARUN = 1
COUNTER STOPS, AFIN = 1
CPU READS RESULT OUT OF SCIADAT
CPU READS RESULT OUT OF SCIADAT
Chapter 15 System Integration Module (SIM)
15.1 Introduction
This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microconroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 15-1. Table 15-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals: - Stop/wait/reset/break entry and recovery - Internal clock control * Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout * Interrupt arbitration Table 15-1 shows the internal signal names used in this section. Table 15-1. Signal Name Conventions
Signal Name CGMXCLK CGMOUT IAB IDB PORRST IRST R/W Description Selected clock source from internal clock generator module (ICG) Clock output from ICG module (Bus clock = CGMOUT divided by two) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 177
System Integration Module (SIM)
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO ICG) SIM COUNTER CGMXCLK (FROM ICG)
CGMOUT (FROM ICG) /2
VDD INTERNAL PULLUP DEVICE RESET PIN LOGIC
CLOCK CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
FORCED MONITOR MODE ENTRY POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 15-1. SIM Block Diagram
Addr. $FE00 Register Name SIM Break Status Register Read: (SBSR) Write: See page 191. Reset: SIM Reset Status Register Read: (SRSR) Write: See page 192. POR: Read: SIM Upper Byte Address Write: Register (SUBAR) Reset: Bit 7 R 0 POR 1 R 6 R 0 PIN 0 R 5 R 0 COP 0 R 4 R 0 ILOP 0 R 3 R 0 ILAD 0 R 2 R 0 MODRST 0 R 1 SBSW NOTE 0 LVI 0 R Bit 0 R 0 0 0 R
Note: Writing a 0 clears SBSW. $FE01
$FE02
Figure 15-2. SIM I/O Register Summary
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 178 Freescale Semiconductor
SIM Bus Clock Control and Generation Addr. $FE03 Register Name SIM Break Flag Control Read: Register (SBFCR) Write: See page 193. Reset: Interrupt Status Read: Register 1 (INT1) Write: See page 187. Reset: Interrupt Status Read: Register 2 (INT2) Write: See page 188. Reset: Interrupt Status Read: Register 3 (INT3) Write: See page 188. Reset: Bit 7 BCFE 0 IF6 R 0 IF14 R 0 0 R 0 IF5 R 0 IF13 R 0 0 R 0 = Unimplemented IF4 R 0 IF12 R 0 0 R 0 IF3 R 0 IF11 R 0 0 R 0 R IF2 R 0 IF10 R 0 0 R 0 = Reserved IF1 R 0 IF9 R 0 0 R 0 0 R 0 IF8 R 0 IF16 R 0 0 R 0 IF7 R 0 IF15 R 0 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
$FE04
$FE05
$FE06
Figure 15-2. SIM I/O Register Summary (Continued)
15.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 15-3. This clock originates from either an external oscillator or from the internal clock generator.
COPCLK TBMCLK ECLK CLOCK SELECT CIRCUIT /2 A CGMXCLK CGMOUT
COP PRESCALER TBM PRESCALER SIM COUNTER /2 BUS CLOCK GENERATORS
ICLK ICG GENERATOR CS
B S* *WHEN S = 1, CGMOUT = B
SIM
MONITOR MODE USER MODE
ICG
Figure 15-3. System Clock Signals
15.2.1 Bus Timing
In user mode, the internal bus frequency is the internal clock generator output (CGMXCLK) divided by four.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 179
System Integration Module (SIM)
15.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout.
15.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. See 15.6.2 Stop Mode. In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
15.3 Reset and System Initialization
The MCU has these reset sources: * Power-on reset module (POR) * External reset pin (RST) * Computer operating properly module (COP) * Low-voltage inhibit module (LVI) * Illegal opcode * Illegal address * Forced monitor mode entry reset (MODRST) All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 15.4 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See 15.7 SIM Registers.
15.3.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 15-2 for details. Figure 15-4 shows the relative timing.
CGMOUT RST IAB PC VECT H VECT L
Figure 15-4. External Reset Timing
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 180 Freescale Semiconductor
Reset and System Initialization
15.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. See Figure 15-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 15-6. NOTE For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 15-5. The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.
IRST
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
CGMXCLK
IAB
VECTOR HIGH
Figure 15-5. Internal Reset Timing
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR MODRST
INTERNAL RESET
Figure 15-6. Sources of Internal Reset Table 15-2. PIN Bit Set Timing
Reset Recovery Type POR/LVI All others Actual Number of Cycles 4163 (4096 + 64 + 3) 67 (64 + 3)
15.3.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 181
System Integration Module (SIM)
At power-on, these events occur: * A POR pulse is generated. * The internal reset signal is asserted. * The SIM enables CGMOUT. * Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. * The RST pin is driven low during the oscillator stabilization time. * The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.
OSC1
PORRST 4096 CYCLES CGMXCLK 32 CYCLES 32 CYCLES
CGMOUT
RST IRST
IAB
$FFFE
$FFFF
Figure 15-7. POR Recovery 15.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VTST on the RST pin disables the COP module. 15.3.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the CONFIG1 register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 182 Freescale Semiconductor
SIM Counter
15.3.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. 15.3.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 15.3.2.6 Monitor Mode Entry Module Reset (MODRST) The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are erased ($FF). (See 19.3.1 Functional Description.) When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources.
15.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter is 13 bits long.
15.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine.
15.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the CONFIG1 register. If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared.
15.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. See 15.6.2 Stop Mode for details. The SIM counter is free-running after all reset states. See 15.3.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 183
System Integration Module (SIM)
15.5 Exception Control
Normal, sequential program execution can be changed in three different ways: * Interrupts: - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * Reset * Break interrupts
15.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 15-8 shows interrupt entry timing. Figure 15-9 shows interrupt recovery timing.
MODULE INTERRUPT
I BIT
IAB
DUMMY
SP
SP - 1
SP - 2
SP - 3
SP - 4
VECT H
VECT L
START ADDR
IDB
DUMMY
PC - 1[7:0] PC - 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 15-8. Interrupt Entry Timing
MODULE INTERRUPT
I BIT
IAB
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC
PC + 1
IDB
CCR
A
X
PC - 1 [7:0] PC - 1 [15:8] OPCODE
OPERAND
R/W
Figure 15-9. Interrupt Recovery Timing Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See Figure 15-10.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 184 Freescale Semiconductor
Exception Control
FROM RESET
BREAK I BIT SET? INTERRUPT? NO YES
YES
I BIT SET? NO IRQ INTERRUPT? NO YES
AS MANY INTERRUPTS AS EXIST ON CHIP STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? NO RTI INSTRUCTION? NO
YES
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 15-10. Interrupt Processing 15.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 15-11 demonstrates what happens when two interrupts are pending. If an interrupt
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 185
System Integration Module (SIM)
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 15-11. Interrupt Recognition Example 15.5.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does. 15.5.1.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 15-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 186 Freescale Semiconductor
Exception Control
Table 15-3. Interrupt Sources
Priority Highest Interrupt Source Reset SWI instruction IRQ pin ICG clock monitor TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 channel 1 TIM2 overflow SPI receiver full SPI transmitter empty SCI receive error SCI receive SCI transmit Keyboard ADC conversion complete Lowest Timebase module Interrupt Status Register Flag -- -- I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 I16
Interrupt Status Register 1
Address: Read: Write: Reset: $FE04 Bit 7 I6 R 0 R 6 I5 R 0 = Reserved 5 I4 R 0 4 I3 R 0 3 I2 R 0 2 I1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 15-12. Interrupt Status Register 1 (INT1) I6-I1 -- Interrupt Flags 1-6 These flags indicate the presence of interrupt requests from the sources shown in Table 15-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 and Bit 1 -- Always read 0
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 187
System Integration Module (SIM)
Interrupt Status Register 2
Address: Read: Write: Reset: $FE05 Bit 7 I14 R 0 R 6 I13 R 0 = Reserved 5 I12 R 0 4 I11 R 0 3 I10 R 0 2 I9 R 0 1 I8 R 0 Bit 0 I7 R 0
Figure 15-13. Interrupt Status Register 2 (INT2) I14-I7 -- Interrupt Flags 14-7 These flags indicate the presence of interrupt requests from the sources shown in Table 15-3. 1 = Interrupt request present 0 = No interrupt request present Interrupt Status Register 3
Address: Read: Write: Reset: $FE06 Bit 7 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 I16 R 0 Bit 0 I15 R 0
Figure 15-14. Interrupt Status Register 3 (INT3) Bits 7-2 -- Always read 0 I16-I15 -- Interrupt Flags 16-15 These flags indicate the presence of an interrupt request from the source shown in Table 15-3. 1 = Interrupt request present 0 = No interrupt request present
15.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
15.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output (see Chapter 18 Timer Interface Module (TIM)). The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
15.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR).
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 188 Freescale Semiconductor
Low-Power Modes
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
15.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
15.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 15-15 shows the timing for wait mode entry.
IAB WAIT ADDR WAIT ADDR + 1 SAME SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note:
Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 15-15. Wait Mode Entry Timing A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the CONFIG1 register is 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Figure 15-16 and Figure 15-17 show the timing for WAIT recovery.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 189
System Integration Module (SIM)
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt or break interrupt interrupt
Figure 15-16. Wait Recovery from Interrupt or Break
32 CYCLES IAB $6E0B 32 CYCLES RSTVCTH RST VCTL
IDB
$A6
$A6
$A6
RST
CGMXCLK
Figure 15-17. Wait Recovery from Internal Reset
15.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in CONFIG1. If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. NOTE All applications should use the full stop recovery time by clearing the SSREC bit unless OSCENINSTOP is set in CONFIG2. The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 15-18 shows stop mode entry timing. NOTE To minimize stop current, all pins configured as inputs should be driven to a 1 or 0.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 190 Freescale Semiconductor
SIM Registers
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 15-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 15-19. Stop Mode Recovery from Interrupt
15.7 SIM Registers
The SIM has three memory-mapped registers. Table 15-4 shows the mapping of these registers. Table 15-4. SIM Registers
Address $FE00 $FE01 $FE03 Register SBSR SRSR SBFCR Access Mode User User User
15.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode.
Address: Read: Write: Reset: $FE00 Bit 7 R 0 R 6 R 0 = Reserved 5 R 0 4 R 0 3 R 0 2 R 0 1 SBSW Note(1) 0 Bit 0 R 0
Note: 1. Writing a 0 clears SBSW.
Figure 15-20. SIM Break Status Register (SBSR)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 191
System Integration Module (SIM)
SBSW -- SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt. 0 = Wait mode was not exited by break interrupt.
15.7.2 SIM Reset Status Register
The SRSR register contains flags that show the source of the latest reset. The status register will automatically clear after reading it. A power-on reset sets the POR bit and clears all other bits in the register. All other reset sources set the individual flag bits but do not clear the register. More than one reset source can be flagged at any time depending on the conditions at the time of the internal or external reset. For example, the POR and LVI bits can both be set if the power supply has a slow rise time.
Address: $FE01 Bit 7 Read: Write: Reset: 1 0 = Unimplemented 0 0 0 0 0 0 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 MODRST 1 LVI Bit 0 0
Figure 15-21. SIM Reset Status Register (SRSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST -- Monitor Mode Entry Module Reset Bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ VTST 0 = POR or read of SRSR LVI -- Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 192 Freescale Semiconductor
SIM Registers
15.7.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: Read: Write: Reset: $FE03 Bit 7 BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Figure 15-22. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 193
System Integration Module (SIM)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 194 Freescale Semiconductor
Chapter 16 Serial Peripheral Interface (SPI) Module
16.1 Introduction
This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports.
16.2 Features
Features of the SPI module include: * Full-duplex operation * Master and slave modes * Double-buffered operation with separate transmit and receive registers * Four master mode frequencies (maximum = bus frequency / 2) * Maximum slave mode frequency = bus frequency * Serial clock with programmable polarity and phase * Two separately enabled interrupts: - SPRF (SPI receiver full) - SPTE (SPI transmitter empty) * Mode fault error flag with CPU interrupt capability * Overflow error flag with CPU interrupt capability * Programmable wired-OR mode * I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s)
16.3 Functional Description
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt driven. If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. The following paragraphs describe the operation of the SPI module. Refer to Figure 16-2 for a summary of the SPI I/O registers.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 195
Serial Peripheral Interface (SPI) Module
INTERNAL BUS PORTA M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(3) SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA SERIAL PERIPHERAL INTERFACE MODULE PORTB DDRB PTA7/KBD7- PTA0/KBD0(1) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1)(2) PTC3(1)(2) PTC2(1)(2) PTC1(1)(2) PTC0(1)(2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE2 PTE1/RxD PTE0/TxD
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH MC68HC908GT16 -- 15,872 BYTES MC68HC908GT8 -- 7,680 BYTES USER RAM -- 512 BYTES MONITOR ROM -- 304 BYTES FLASH PROGRAMMING ROUTINES ROM -- 720 BYTES USER FLASH VECTOR SPACE -- 36 BYTES
PTE4/OSC1 PTE3/OSC2
INTERNAL CLOCK GENERATOR MODULE
IRQ(3) VREFH VREFL
MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE
PORTE
MONITOR MODULE DDRE
PORTD
DDRD
PORTC
DDRC
SECURITY MODULE
POWER
MONITOR MODE ENTRY MODULE
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
Figure 16-1. Block Diagram Highlighting SPI Block and Pins
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 196 Freescale Semiconductor
Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER
BUSCLK 7 /2 CLOCK DIVIDER /8 / 32 / 128 CLOCK SELECT 6
SHIFT REGISTER 5 4 3 2 1 0 MISO
MOSI RECEIVE DATA REGISTER PIN CONTROL LOGIC SPSCK CLOCK LOGIC M S SS
SPMSTR
SPE
SPR1
SPR0
SPMSTR
CPHA
CPOL
TRANSMITTER CPU INTERRUPT REQUEST SPI CONTROL RECEIVER/ERROR CPU INTERRUPT REQUEST
MODFEN ERRIE SPTIE SPRIE SPE SPRF SPTE OVRF MODF
SPWOM
Figure 16-2. SPI Module Block Diagram
Addr. $0010 Register Name SPI Control Register Read: (SPCR) Write: See page 211. Reset: SPI Status and Control Read: Register (SPSCR) Write: See page 212. Reset: SPI Data Register Read: (SPDR) Write: See page 214. Reset: Bit 7 SPRIE 0 SPRF 0 R7 T7 R 6 R 0 ERRIE 0 R6 T6 = Reserved 5 SPMSTR 1 OVRF 0 R5 T5 4 CPOL 0 MODF 3 CPHA 1 SPTE 2 SPWOM 0 MODFEN 1 SPE 0 SPR1 0 R1 T1 Bit 0 SPTIE 0 SPR0 0 R0 T0
$0011
$0012
0 1 0 R4 R3 R2 T4 T3 T2 Unaffected by reset = Unimplemented
Figure 16-3. SPI I/O Register Summary
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 197
Serial Peripheral Interface (SPI) Module
16.3.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE In a multi-SPI system, configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See 16.12.1 SPI Control Register. Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI pin under the control of the serial clock. See Figure 16-4.
MASTER MCU SLAVE MCU
SHIFT REGISTER
MISO MOSI SPSCK
MISO MOSI SPSCK SS
SHIFT REGISTER
BAUD RATE GENERATOR
SS
VDD
Figure 16-4. Full-Duplex Master-Slave Connections The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 16.12.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master's MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Writing to the SPI data register (SPDR) clears SPTE.
16.3.2 Slave Mode
The SPI operates in slave mode when SPMSTR is clear. In slave mode, the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. See 16.6.2 Mode Fault Error. In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register, and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 198 Freescale Semiconductor
Transmission Formats
The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the MISO pin. Data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. See 16.4 Transmission Formats. NOTE SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge.
16.4 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate multiple-master bus contention.
16.4.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. NOTE Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI enable bit (SPE).
16.4.2 Transmission Format When CPHA = 0
Figure 16-5 shows an SPI transmission in which CPHA = 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 199
Serial Peripheral Interface (SPI) Module
input (SS) is low, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 16.6.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave's SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 16-6. When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission.
SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE SS; TO SLAVE CAPTURE STROBE MSB MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 LSB LSB
1
2
3
4
5
6
7
8
Figure 16-5. Transmission Format (CPHA = 0)
MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1
BYTE 1
BYTE 2
BYTE 3
Figure 16-6. CPHA/SS Timing
16.4.3 Transmission Format When CPHA = 1
Figure 16-7 shows an SPI transmission in which CPHA = 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is low, so that only the selected
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 200 Freescale Semiconductor
Transmission Formats
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 16.6.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line.
SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE SS; TO SLAVE CAPTURE STROBE MSB MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 LSB LSB
1
2
3
4
5
6
7
8
Figure 16-7. Transmission Format (CPHA = 1) When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission.
16.4.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. (See Figure 16-8.) The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and SPMSTR bits are set. Since the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 16-8. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 201
Serial Peripheral Interface (SPI) Module
WRITE TO SPDR BUS CLOCK MOSI SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 1 2 3
INITIATION DELAY
MSB
BIT 6
BIT 5
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST SPSCK = BUS CLOCK / 128; 128 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK / 32; 32 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK / 8; 8 POSSIBLE START POINTS LATEST LATEST SPSCK = BUS CLOCK / 2; 2 POSSIBLE START POINTS
Figure 16-8. Transmission Start Delay (Master)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 202 Freescale Semiconductor
Queuing Transmission Data
16.5 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when SPTE is high. Figure 16-9 shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0).
WRITE TO SPDR SPTE SPSCK CPHA:CPOL = 1:0 MOSI
1 2
3 5
8 10
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 654 654321 654321 BYTE 1 BYTE 2 BYTE 3 4 6 7 7 CPU READS SPDR, CLEARING SPRF BIT. 8 CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT. 9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT. 9 11 12
SPRF READ SPSCR READ SPDR 1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 3 CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 AND CLEARING SPTE BIT. 4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 5 BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 6 CPU READS SPSCR WITH SPRF BIT SET.
Figure 16-9. SPRF/SPTE CPU Interrupt Timing The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. Also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. SPTE indicates when the next write can occur.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 203
Serial Peripheral Interface (SPI) Module
16.6 Error Conditions
The following flags signal SPI error conditions: * Overflow (OVRF) -- Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register. * Mode fault error (MODF) -- The MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
16.6.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs in the middle of SPSCK cycle 7 (see Figure 16-5 and Figure 16-7.) If an overflow occurs, all data received after the overflow and before the OVRF bit is cleared does not transfer to the receive data register and does not set the SPI receiver full bit (SPRF). The unread data that transferred to the receive data register before the overflow occurred can still be read. Therefore, an overflow error always indicates the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading the SPI data register. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector (see Figure 16-12.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 16-10 shows how it is possible to miss an overflow. The first part of Figure 16-10 shows how it is possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR are read.
BYTE 1 1 BYTE 2 4 BYTE 3 6 BYTE 4 8
SPRF
OVRF READ SPSCR READ SPDR 1 2 3 4 2 5
3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. 5 6 7 8
7 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Figure 16-10. Missed Read of Overflow Condition
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 204 Freescale Semiconductor
Error Conditions
In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 16-11 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit.
BYTE 1 SPI RECEIVE COMPLETE SPRF OVRF READ SPSCR READ SPDR 1 2 3 4 5 6 7 2 3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. BYTE 2 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 4 6 8 8 9 9 10 12 13 14 1 BYTE 2 5 BYTE 3 7 BYTE 4 11
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
Figure 16-11. Clearing SPRF When OVRF Interrupt Is Not Enabled
16.6.2 Mode Fault Error
Setting SPMSTR selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR. To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if: * The SS pin of a slave SPI goes high during a transmission * The SS pin of a master SPI goes low at any time For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 16-12.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 205
Serial Peripheral Interface (SPI) Module
In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes low. A mode fault in a master SPI causes the following events to occur: * If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. * The SPE bit is cleared. * The SPTE bit is set. * The SPI state counter is cleared. * The data direction register of the shared I/O port regains control of port drivers. NOTE To prevent bus contention with another master SPI after a mode fault error, clear all SPI bits of the data direction register of the shared I/O port before enabling the SPI. When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit. When CPHA = 1, the transmission begins when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns to its idle level following the shift of the last data bit. See See 16.4 Transmission Formats. NOTE Setting the MODF flag does not clear the SPMSTR bit. SPMSTR has no function when SPE = 0. Reading SPMSTR when MODF = 1 shows the difference between a MODF occurring when the SPI is a master and when it is a slave. NOTE When CPHA = 0, a MODF occurs if a slave is selected (SS is low) and later unselected (SS is high) even if no SPSCK is sent to that slave. This happens because SS low indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), MODF generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by clearing the SPE bit of the slave. NOTE A high on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 206 Freescale Semiconductor
Interrupts
16.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. See Table 16-1. Table 16-1. SPI Interrupts
Flag SPTE -- Transmitter empty SPRF -- Receiver full OVRF -- Overflow MODF -- Mode fault Request SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1) SPI receiver CPU interrupt request (SPRIE = 1) SPI receiver/error interrupt request (ERRIE = 1) SPI receiver/error interrupt request (ERRIE = 1)
Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1). The SPI receiver interrupt enable bit (SPRIE) enables SPRF to generate receiver CPU interrupt requests, regardless of the state of SPE. See Figure 16-12.
SPTE
SPTIE
SPE SPI TRANSMITTER CPU INTERRUPT REQUEST
SPRIE
SPRF
SPI RECEIVER/ERROR ERRIE MODF OVRF CPU INTERRUPT REQUEST
Figure 16-12. SPI Interrupt Request Generation The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests. The following sources in the SPI status and control register can generate CPU interrupt requests: * SPI receiver full bit (SPRF) -- SPRF becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request. * SPI transmitter empty (SPTE) -- SPTE becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE generates an SPTE CPU interrupt request.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 207
Serial Peripheral Interface (SPI) Module
16.8 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is 0. Whenever SPE is 0, the following occurs: * The SPTE flag is set. * Any transmission currently in progress is aborted. * The shift register is cleared. * The SPI state counter is cleared, making it ready for a new complete transmission. * All the SPI port logic is defaulted back to being general-purpose I/O. These items are reset only by a system reset: * All control bits in the SPCR register * All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) * The status flags SPRF, OVRF, and MODF By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission. By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
16.9 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
16.9.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). See 16.7 Interrupts.
16.9.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset.
16.10 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. BCFE in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See Chapter 15 System Integration Module (SIM). To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 208 Freescale Semiconductor
I/O Signals
To protect status bits during the break state, write a 0 to BCFE. With BCFE at 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is 0. After the break, doing the second step clears the status bit. Since the SPTE bit cannot be cleared during a break with BCFE cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. Therefore, a write to the SPDR in break mode with BCFE cleared has no effect.
16.11 I/O Signals
The SPI module has four I/O pins: * MISO -- Master input/slave output * MOSI -- Master output/slave input * SPSCK -- Serial clock * SS -- Slave select
16.11.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is 0 and its SS pin is low. To support a multiple-slave system, a high on the SS pin puts the MISO pin in a high-impedance state. When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I/O port.
16.11.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port.
16.11.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 209
Serial Peripheral Interface (SPI) Module
16.11.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. (See 16.4 Transmission Formats.) Since it is used to indicate the start of a transmission, SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low between transmissions for the CPHA = 1 format. See Figure 16-13. When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of SS from creating a MODF error. See 16.12.2 SPI Status and Control Register.
MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1
BYTE 1
BYTE 2
BYTE 3
Figure 16-13. CPHA/SS Timing NOTE A high on the SS pin of a slave SPI puts the MISO pin in a high-impedance state. The slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 16.6.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If MODFEN is 0 for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port. When MODFEN is 1, SS is an input-only pin to the SPI regardless of the state of the data direction register of the shared I/O port. The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register. See Table 16-2
.
Table 16-2. SPI Configuration
SPE 0 1 1 1 SPMSTR X(1)) 0 1 1 MODFEN X X 0 1 SPI Configuration Not enabled Slave Master without MODF Master with MODF Function of SS Pin General-purpose I/O; SS ignored by SPI Input-only to SPI General-purpose I/O; SS ignored by SPI Input-only to SPI
1. X = Don't care
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 210 Freescale Semiconductor
I/O Registers
16.12 I/O Registers
Three registers control and monitor SPI operation: * SPI control register (SPCR) * SPI status and control register (SPSCR) * SPI data register (SPDR)
16.12.1 SPI Control Register
The SPI control register: * Enables SPI module interrupt requests * Configures the SPI module as master or slave * Selects serial clock polarity and phase * Configures the SPSCK, MOSI, and MISO pins as open-drain outputs * Enables the SPI module
Address: $0010 Bit 7 Read: Write: Reset: SPRIE 0 R 6 R 0 = Reserved 5 SPMSTR 1 4 CPOL 0 3 CPHA 1 2 SPWOM 0 1 SPE 0 Bit 0 SPTIE 0
Figure 16-14. SPI Control Register (SPCR) SPRIE -- SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled SPMSTR -- SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode CPOL -- Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 16-5 and Figure 16-7.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit. CPHA -- Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 16-5 and Figure 16-7.) To transmit data between SPI modules, the SPI modules must have identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be high between bytes. (See Figure 16-13.) Reset sets the CPHA bit.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 211
Serial Peripheral Interface (SPI) Module
SPWOM -- SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE -- SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 16.8 Resetting the SPI.) Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE-- SPI Transmit Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled
16.12.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions: * Receive data register full * Failure to clear SPRF bit before next byte is received (overflow error) * Inconsistent logic level on SS pin (mode fault error) * Transmit data register empty The SPI status and control register also contains bits that perform these functions: * Enable error interrupts * Enable mode fault error detection * Select master SPI baud rate
Address: $0011 Bit 7 Read: Write: Reset: 0 SPRF 6 ERRIE 0 5 OVRF 0 4 MODF 0 3 SPTE 1 2 MODFEN 0 1 SPR1 0 Bit 0 SPR0 0
= Unimplemented
Figure 16-15. SPI Status and Control Register (SPSCR) SPRF -- SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 212 Freescale Semiconductor
I/O Registers
ERRIE -- Error Interrupt Enable Bit This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF -- Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the receive data register. Reset clears the OVRF bit. 1 = Overflow 0 = No overflow MODF -- Mode Fault Bit This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with MODFEN set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set. Clear MODF by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE -- SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request if SPTIE in the SPI control register is set also. NOTE Do not write to the SPI data register unless SPTE is high. During an SPTE CPU interrupt, the CPU clears SPTE by writing to the transmit data register. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty MODFEN -- Mode Fault Enable Bit This read/write bit, when set, allows the MODF flag to be set. If the MODF flag is set, clearing MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is 0, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is 1, then the SS pin is not available as a general-purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN. See 16.11.4 SS (Slave Select). If the MODFEN bit is 0, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. See 16.6.2 Mode Fault Error.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 213
Serial Peripheral Interface (SPI) Module
SPR1 and SPR0 -- SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in Table 16-3. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 16-3. SPI Master Baud Rate Selection
SPR1 and SPR0 00 01 10 11 Baud Rate Divisor (BD) 2 8 32 128
Use this formula to calculate the SPI baud rate: Baud rate = BUSCLK BD
16.12.3 SPI Data Register
The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. See Figure 16-2.
Address: $0012 Bit 7 Read: Write: Reset: R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0
Unaffected by reset
Figure 16-16. SPI Data Register (SPDR) R7-R0/T7-T0 -- Receive/Transmit Data Bits NOTE Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 214 Freescale Semiconductor
Chapter 17 Timebase Module (TBM)
17.1 Introduction
This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external crystal clock. This TBM version uses 15 divider stages, eight of which are user selectable.
17.2 Features
Features of the TBM include: * Software programmable 1-Hz, 4-Hz, 16-Hz, 256-Hz, 512-Hz, 1024-Hz, 2048-Hz, and 4096-Hz periodic interrupt using external 32.768-kHz crystal * User selectable oscillator clock source enable during stop mode to allow periodic wakeup from stop
17.3 Functional Description
NOTE This module is designed for a 32.768-kHz oscillator. This module can generate a periodic interrupt by dividing the clock TBMCLK. The counter is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 17-1, starts counting when the TBON bit is set. When the counter overflows at the tap selected by TBR2:TBR0, the TBIF bit gets set. If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact period.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 215
Timebase Module (TBM)
TBON
TBMCLK
/2
/2
/2 /8
/2
/2 / 16
/2 / 32
/2 / 64 / 128
TBMINT
/2
/2
/2
/2
/2 / 2048
/2
/2 / 8192
/2 / 32768
TACK
TBR0
TBR2
TBR1
TBIF 000 001 010 011 100 101 110 111 SEL R
TBIE
Figure 17-1. Timebase Block Diagram
17.4 Timebase Register Description
The timebase has one register, the timebase control register (TBCR), which is used to enable the timebase interrupts and set the rate.
Address: Read: Write: Reset: 0 $001C Bit 7 TBIF 6 TBR2 0 5 TBR1 0 4 TBR0 0 3 0 TACK 0 R 2 TBIE 0 = Reserved 1 TBON 0 Bit 0 R 0
= Unimplemented
Figure 17-2. Timebase Control Register (TBCR) TBIF -- Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over. 1 = Timebase interrupt pending 0 = Timebase interrupt not pending
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 216 Freescale Semiconductor
Interrupts
TBR2:TBR0 -- Timebase Rate Selection These read/write bits are used to select the rate of timebase interrupts as shown in Table 17-1. Table 17-1. Timebase Rate Selection for OSC1 = 32.768 kHz
TBR2 0 0 0 0 1 1 1 1 TBR1 0 0 1 1 0 0 1 1 TBR0 0 1 0 1 0 1 0 1 Divider 32768 8192 2048 128 64 32 16 8 Timebase Interrupt Rate Hz 1 4 16 256 512 1024 2048 4096 ms 1000 250 62.5 ~ 3.9 ~2 ~1 ~0.5 ~0.24
NOTE Do not change TBR2:TBR0 bits while the timebase is enabled (TBON = 1). TACK -- Timebase ACKnowledge The TACK bit is a write-only bit and always reads as 0. Writing a 1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a 0 to this bit has no effect. 1 = Clear timebase interrupt flag 0 = No effect TBIE -- Timebase Interrupt Enabled This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the TBIE bit. 1 = Timebase interrupt enabled 0 = Timebase interrupt disabled TBON -- Timebase Enabled This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption when its function is not necessary. The counter can be initialized by clearing and then setting this bit. Reset clears the TBON bit. 1 = Timebase enabled 0 = Timebase disabled and the counter initialized to 0s
17.5 Interrupts
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2:TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing a 1 to the TACK bit.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 217
Timebase Module (TBM)
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
17.6.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, reduce the power consumption by stopping the timebase before enabling the WAIT instruction.
17.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register. The timebase module can be used in this mode to generate a periodic wakeup from stop mode. If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during STOP mode. In stop mode the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the STOP instruction.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 218 Freescale Semiconductor
Chapter 18 Timer Interface Module (TIM)
18.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 18-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC T[1,2]CH1 CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC T[1,2]CH0 PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
Figure 18-1. TIM Block Diagram
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 219
Timer Interface Module (TIM)
INTERNAL BUS PORTA M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(3) SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA SERIAL PERIPHERAL INTERFACE MODULE PORTB DDRB PTA7/KBD7- PTA0/KBD0(1) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1)(2) PTC3(1)(2) PTC2(1)(2) PTC1(1)(2) PTC0(1)(2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE2 PTE1/RxD PTE0/TxD
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH MC68HC908GT16 -- 15,872 BYTES MC68HC908GT8 -- 7,680 BYTES USER RAM -- 512 BYTES MONITOR ROM -- 304 BYTES FLASH PROGRAMMING ROUTINES ROM -- 720 BYTES USER FLASH VECTOR SPACE -- 36 BYTES
PTE4/OSC1 PTE3/OSC2
INTERNAL CLOCK GENERATOR MODULE
IRQ(3) VREFH VREFL
MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE
PORTE
MONITOR MODULE DDRE
PORTD
DDRD
PORTC
DDRC
SECURITY MODULE
POWER
MONITOR MODE ENTRY MODULE
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
Figure 18-2. Block Diagram Highlighting TIM Blocks and Pins
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 220 Freescale Semiconductor
Features
18.2 Features
Features of the TIM include: * Two input capture/output compare channels: - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action * Buffered and unbuffered pulse-width-modulation (PWM) signal generation * Programmable TIM clock input with 7-frequency internal bus clock prescaler selection * Free-running or modulo up-count operation * Toggle any channel pin on overflow * TIM counter stop and reset bits
18.3 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where "1" is used to indicate TIM1 and "2" is used to indicate TIM2. The two TIMs share four I/O pins with four port D I/O port pins. NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
18.4 Functional Description
Figure 18-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels (per timer) are programmable independently as input capture or output compare channels. If a channel is configured as input capture, then an internal pullup device may be enabled for that channel. See 12.5.3 Port D Input Pullup Enable Register. Figure 18-3 summarizes the timer registers. NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC and T2SC.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 221
Timer Interface Module (TIM) Addr. $0020 Register Name Timer 1 Status and Control Read: Register (T1SC) Write: See page 229. Reset: Timer 1 Counter Read: Register High (T1CNTH) Write: See page 230. Reset: Timer 1 Counter Read: Register Low (T1CNTL) Write: See page 230. Reset: Timer 1 Counter Modulo Read: Register High (T1MODH) Write: See page 231. Reset: Timer 1 Counter Modulo Read: Register Low (T1MODL) Write: See page 231. Reset: Bit 7 TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 6 TOIE 0 14 0 6 0 14 1 6 1 CH0IE 0 14 5 TSTOP 1 13 0 5 0 13 1 5 1 MS0B 0 13 4 0 TRST 0 12 0 4 0 12 1 4 1 MS0A 0 12 0 11 0 3 0 11 1 3 1 ELS0B 0 11 3 0 2 PS2 0 10 0 2 0 10 1 2 1 ELS0A 0 10 1 PS1 0 9 0 1 0 9 1 1 1 TOV0 0 9 Bit 0 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$0021
$0022
$0023
$0024
Timer 1 Channel 0 Status and Read: $0025 Control Register (T1SC0) Write: See page 231. Reset: $0026 Timer 1 Channel 0 Read: Register High (T1CH0H) Write: See page 234. Reset: Timer 1 Channel 0 Read: Register Low (T1CH0L) Write: See page 234. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0027
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 0 13 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
Timer 1 Channel 1 Status and Read: $0028 Control Register (T1SC1) Write: See page 232. Reset: $0029 Timer 1 Channel 1 Read: Register High (T1CH1H) Write: See page 234. Reset: Timer 1 Channel 1 Read: Register Low (T1CH1L) Write: See page 234. Reset: Timer 2 Status and Control Read: Register (T2SC) Write: See page 229. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$002A
Indeterminate after reset TOF 0 0 TOIE 0 = Unimplemented TSTOP 1 0 TRST 0 0 0 PS2 0 PS1 0 PS0 0
$002B
Figure 18-3. TIM I/O Register Summary (Sheet 1 of 2)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 222 Freescale Semiconductor
Functional Description Addr. $002C Register Name Timer 2 Counter Read: Register High (T2CNTH) Write: See page 230. Reset: Timer 2 Counter Read: Register Low (T2CNTL) Write: See page 230. Reset: Timer 2 Counter Modulo Read: Register High (T2MODH) Write: See page 231. Reset: Timer 2 Counter Modulo Read: Register Low (T2MODL) Write: See page 231. Reset: Bit 7 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 6 14 0 6 0 14 1 6 1 CH0IE 0 14 5 13 0 5 0 13 1 5 1 MS0B 0 13 4 12 0 4 0 12 1 4 1 MS0A 0 12 3 11 0 3 0 11 1 3 1 ELS0B 0 11 2 10 0 2 0 10 1 2 1 ELS0A 0 10 1 9 0 1 0 9 1 1 1 TOV0 0 9 Bit 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$002D
$002E
$002F
Timer 2 Channel 0 Status and Read: $0030 Control Register (T2SC0) Write: See page 231. Reset: $0031 Timer 2 Channel 0 Read: Register High (T2CH0H) Write: See page 234. Reset: Timer 2 Channel 0 Read: Register Low (T2CH0L) Write: See page 234. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0032
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 0 13 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
Timer 2 Channel 1 Status and Read: $0033 Control Register (T2SC1) Write: See page 232. Reset: $0034 Timer 2 Channel 1 Read: Register High (T2CH1H) Write: See page 234. Reset: Timer 2 Channel 1 Read: Register Low (T2CH1L) Write: See page 234. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0035
Indeterminate after reset = Unimplemented
Figure 18-3. TIM I/O Register Summary (Sheet 2 of 2)
18.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the TIM clock source.
18.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 223
Timer Interface Module (TIM)
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.
18.4.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 18.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 18.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. * When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 18.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 224 Freescale Semiconductor
Functional Description
18.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 18-4 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 18.9.1 TIM Status and Control Register. The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%.
OVERFLOW OVERFLOW OVERFLOW
PERIOD
PULSE WIDTH TCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 18-4. PWM Period and Pulse Width 18.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 18.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 225
Timer Interface Module (TIM)
*
When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
18.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 18.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 18-2.) b. Write 1 to the toggle-on-overflow bit, TOVx.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 226 Freescale Semiconductor
Interrupts
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 18-2.) NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 18.9.4 TIM Channel Status and Control Registers.)
18.5 Interrupts
The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. * TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register.
18.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
18.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 227
Timer Interface Module (TIM)
18.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
18.7 TIM During Break Interrupts
A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See 15.7.3 SIM Break Flag Control Register. To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the second step clears the status bit.
18.8 I/O Signals
Port D shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0, and T2CH1 as described in 18.3 Pin Name Conventions. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.
18.9 I/O Registers
NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC AND T2SC. These I/O registers control and monitor operation of the TIM: * TIM status and control register (TSC) * TIM counter registers (TCNTH:TCNTL) * TIM counter modulo registers (TMODH:TMODL) * TIM channel status and control registers (TSC0, TSC1) * TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 228 Freescale Semiconductor
I/O Registers
18.9.1 TIM Status and Control Register
The TIM status and control register (TSC): * Enables TIM overflow interrupts * Flags TIM overflows * Stops the TIM counter * Resets the TIM counter * Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B Bit 7 Read: Write: Reset: TOF 0 0 6 TOIE 0 = Unimplemented 5 TSTOP 1 4 0 TRST 0 0 3 0 2 PS2 0 1 PS1 0 Bit 0 PS0 0
Figure 18-5. TIM Status and Control Register (TSC) TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 229
Timer Interface Module (TIM)
PS[2:0] -- Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 18-1 shows. Reset clears the PS[2:0] bits. Table 18-1. Prescaler Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal bus clock / 1 Internal bus clock / 2 Internal bus clock / 4 Internal bus clock / 8 Internal bus clock / 16 Internal bus clock / 32 Internal bus clock / 64 Not available
18.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Figure 18-6. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Figure 18-7. TIM Counter Registers Low (TCNTL)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 230 Freescale Semiconductor
I/O Registers
18.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: T1MODH, $0023 and T2MODH, $002E Bit 7 Read: Write: Reset: Bit 15 1 6 14 1 5 13 1 4 12 1 3 11 1 2 10 1 1 9 1 Bit 0 Bit 8 1
Figure 18-8. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $0024 and T2MODL, $002F Bit 7 Read: Write: Reset: Bit 7 1 6 6 1 5 5 1 4 4 1 3 3 1 2 2 1 1 1 1 Bit 0 Bit 0 1
Figure 18-9. TIM Counter Modulo Register Low (TMODL) NOTE Reset the TIM counter before writing to the TIM counter modulo registers.
18.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers: * Flags input captures and output compares * Enables input capture and output compare interrupts * Selects input capture, output compare, or PWM operation * Selects high, low, or toggling output on output compare * Selects rising edge, falling edge, or any edge as the active input capture trigger * Selects output toggling on TIM overflow * Selects 0% and 100% PWM duty cycle * Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030 Bit 7 Read: Write: Reset: CH0F 0 0 6 CH0IE 0 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0
Figure 18-10. TIM Channel 0 Status and Control Register (TSC0)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 231
Timer Interface Module (TIM) Address: T1SC1, $0028 and T2SC1, $0033 Bit 7 Read: Write: Reset: CH1F 0 0 6 CH1IE 0 = Unimplemented 5 0 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0
Figure 18-11. TIM Channel 1 Status and Control Register (TSC1) CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:A 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 18-2. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. See Table 18-2. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC).
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 232 Freescale Semiconductor
I/O Registers
Table 18-2. Mode, Edge, and Level Selection
MSxB X X 0 0 0 0 0 0 0 1 1 1 MSxA 0 1 0 0 0 1 1 1 1 X X X ELSxB 0 0 0 1 1 0 0 1 1 0 1 1 ELSxA 0 0 1 0 1 0 1 0 1 1 0 1 Buffered output compare or buffered PWM Output compare or PWM Input capture Mode Output preset Configuration Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Software compare only Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare
ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is available as a general-purpose I/O pin. Table 18-2 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. NOTE Before enabling a TIM channel register for input capture operation, make sure that the PTD/TCHx pin is stable for at least two bus clocks. TOVx -- Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow. NOTE When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 18-12 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 233
Timer Interface Module (TIM)
OVERFLOW PERIOD TCHx OVERFLOW OVERFLOW OVERFLOW OVERFLOW
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 18-12. CHxMAX Latency
18.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: T1CH0H, $0026 and T2CH0H, $0031 Bit 7 6 5 4 3 Read: Bit 15 14 13 12 11 Write: Reset: Indeterminate after reset 2 10 1 9 Bit 0 Bit 8
Figure 18-13. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032 Bit 7 6 5 Read: Bit 7 6 5 Write: Reset: 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Indeterminate after reset
Figure 18-14. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029 and T2CH1H, $0034 Bit 7 6 5 4 3 Read: Bit 15 14 13 12 11 Write: Reset: Indeterminate after reset 2 10 1 9 Bit 0 Bit 8
Figure 18-15. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A and T2CH1L, $0035 Bit 7 6 5 4 3 Read: Bit 7 6 5 4 3 Write: Reset: Indeterminate after reset 2 2 1 1 Bit 0 Bit 0
Figure 18-16. TIM Channel 1 Register Low (TCH1L)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 234 Freescale Semiconductor
Chapter 19 Development Support
19.1 Introduction
This section describes the break module, the monitor module (MON), and the monitor mode entry methods.
19.2 Break Module (BRK)
This section describes the break module (BRK). The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. Features of the break module include: * Accessible input/output (I/O) registers during the break interrupt * Central processor unit (CPU) generated break interrupts * Software-generated break interrupts * Computer operating properly (COP) disabling during break interrupts
19.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the system integration module (SIM). The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * A CPU generated address (the address in the program counter) matches the contents of the break address registers. * Software writes a 1 to the BRKA bit in the break status and control register. When a CPU generated address matches the contents of the break address registers, the break interrupt is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. Figure 19-2 shows the structure of the break module.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 235
Development Support
INTERNAL BUS PORTA M68HC08 CPU DDRA CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(3) SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA SERIAL PERIPHERAL INTERFACE MODULE PORTB DDRB PTA7/KBD7- PTA0/KBD0(1) PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1)(2) PTC3(1)(2) PTC2(1)(2) PTC1(1)(2) PTC0(1)(2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE2 PTE1/RxD PTE0/TxD
CONTROL AND STATUS REGISTERS -- 64 BYTES USER FLASH MC68HC908GT16 -- 15,872 BYTES MC68HC908GT8 -- 7,680 BYTES USER RAM -- 512 BYTES MONITOR ROM -- 304 BYTES FLASH PROGRAMMING ROUTINES ROM -- 720 BYTES USER FLASH VECTOR SPACE -- 36 BYTES
PTE4/OSC1 PTE3/OSC2
INTERNAL CLOCK GENERATOR MODULE
IRQ(3) VREFH VREFL
MEMORY MAP MODULE CONFIGURATION REGISTER 1 MODULE CONFIGURATION REGISTER 2 MODULE
PORTE
MONITOR MODULE DDRE
PORTD
DDRD
PORTC
DDRC
SECURITY MODULE
POWER
MONITOR MODE ENTRY MODULE
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
Figure 19-1. Block Diagram Highlighting BRK and MON Blocks
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 236 Freescale Semiconductor
Break Module (BRK)
IAB15-IAB8
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB15-IAB0 CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BREAK
IAB7-IAB0
Figure 19-2. Break Module Block Diagram
Addr.
Register Name Read: SIM Break Status Register (SBSR) Write: See page 240. Reset:
Bit 7 0 R 0
6 0 R 0
5 0 R 0
4 1 R 1
3 0 R 0
2 0 R 0
1 SBSW NOTE 0
Bit 0 0 R 0
$FE00
Note: Writing a 0 clear SBSW. Read: SIM Break Flag Control Register (SBFCR) Write: See page 240. Reset: BCFE 0 Bit 15 0 Bit 7 0 BRKE 0 14 0 6 0 BRKA 0 = Unimplemented 0 0 R 0 = Reserved 0 0 0 13 0 5 0 0 12 0 4 0 0 11 0 3 0 0 10 0 2 0 0 9 0 1 0 0 Bit 8 0 Bit 0 0 0 R R R R R R R
$FE03
Read: Break Address Register High $FE09 (BRKH) Write: See page 239. Reset: Read: Break Address Register Low $FE0A (BRKL) Write: See page 239. Reset: Read: Break Status and Control Register (BRKSCR) Write: See page 239. Reset:
$FE0B
Figure 19-3. I/O Register Summary
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 237
Development Support
When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: * * * * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. When a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction is executed.
The break interrupt timing is:
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can be generated continuously. CAUTION A break address should be placed at the address of the instruction opcode. When software does not change the break address and clears the BRKA bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers. 19.2.1.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 15.7.3 SIM Break Flag Control Register and the Break Interrupts subsection for each module. 19.2.1.2 TIM1 and TIM2 During Break Interrupts A break interrupt stops the timer counters. 19.2.1.3 COP During Break Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin.
19.2.2 Break Module Registers
These registers control and monitor operation of the break module: * * * * * Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL) SIM break status register (SBSR) SIM break flag control register (SBFCR)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 238 Freescale Semiconductor
Break Module (BRK)
19.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits.
Address: Read: Write: Reset: $FE0B Bit 7 BRKE 0 6 BRKA 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 19-4. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = (When read) Break address match 0 = (When read) No break address match 19.2.2.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Address: Read: Write: Reset: $FE09 Bit 7 Bit 15 0 6 14 0 5 13 0 4 12 0 3 11 0 2 10 0 1 9 0 Bit 0 Bit 8 0
Figure 19-5. Break Address Register High (BRKH)
Address: Read: Write: Reset: $FE0A Bit 7 Bit 7 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0 Bit 0 Bit 0 0
Figure 19-6. Break Address Register Low (BRKL)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 239
Development Support
19.2.2.3 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode.
Address: $FE00 Bit 7 Read: Write: Reset: R = Reserved 1. Writing a 0 clears SBSW. R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note(1) 0 Bit 0 R
Figure 19-7. SIM Break Status Register (SBSR) SBSW -- SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt 19.2.2.4 Break Flag Control Register The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: Read: Write: Reset: $FE03 Bit 7 BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
Figure 19-8. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 240 Freescale Semiconductor
Monitor Module (MON)
19.3 Monitor Module (MON)
The monitor module allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. Features of the monitor module include: * * * * * * * * * * Normal user-mode pin functionality One pin dedicated to serial communication between monitor read-only memory (ROM) and host computer Standard mark/space non-return-to-zero (NRZ) communication with host computer Execution of code in random-access memory (RAM) or FLASH FLASH memory security feature(1) FLASH memory programming interface External 4.92 MHz or 9.83 MHz clock used to generate internal frequency of 2.4576 MHz Optional ICG mode of operation (no external clock or high voltage) Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) Normal monitor mode entry if high voltage is applied to IRQ
19.3.1 Functional Description
Figure 19-9 shows a simplified monitor mode entry flowchart. The monitor ROM receives and executes commands from a host computer. Figure 19-10, Figure 19-11, and Figure 19-12 show example circuits used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. The monitor code has been updated from previous versions of the monitor code to allow the ICG to generate the internal clock. This option, which is selected when IRQ is held low out of reset, is intended to support serial communication/ programming at 9600 baud in monitor mode by using the ICG, and the ICG user trim value ICGTR5 (if programmed) to generate the desired internal frequency (2.4576 MHz). If ICGTR5 is not programmed (i.e., the value is $FF) then the ICG will operate at a nominal (untrimmed) 2.45 MHz and communications will be nominally at 9600 baud but the untrimmed rate may cause difficulties with hosts which cannot automatically adjust their data rates to match. Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value is not $FFFF) because entry into monitor mode in this case requires VTST on IRQ.
1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 241
Development Support
POR RESET
NO
IRQ = VTST?
YES
CONDITIONS FROM Table 19-1
PTA0 = 1, RESET BLANK? YES FORCED MONITOR MODE
NO
PTA0 = 1, PTC0 = 1, PTC1 = 0, AND PTC3 = 1? YES NORMAL USER MODE NORMAL MONITOR MODE
NO
FACTORY USE ONLY
SEND 8 BYTES SECURITY
IS RESET POR? NO
YES
YES
ARE ALL SECURITY BYTES CORRECT?
NO
ENABLE FLASH
DISABLE FLASH
MONITOR MODE ENTRY
DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED)
EXECUTE MONITOR CODE
YES
DOES RESET OCCUR?
NO
Figure 19-9. Simplified Monitor Mode Entry Flowchart
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 242 Freescale Semiconductor
Monitor Module (MON)
VDD RST 0.1 F VDDA VDD 0.1 F
MAX232 4 1 F + 5 4 1 F + 5 C2- DB9 2 3 5 7 8 10 9 C1+ 16
VDD
N.C.
OSC2
N.C. 0.1 F 15 VTST 2 k + 10 k 74HC125 5 6 74HC125 3 2 1 4 VDD
OSC1 IRQ
PTC0
N.C.
C1- C2+
PTC3
N.C.
V+ 2 V- 6 1 F +
PTC1
N.C.
PTA0
VSS VSSA
Figure 19-10. Forced Monitor Mode (Low)
VDD RST 0.1 F MAX232 4 1 F + 5 4 1 F + 5 C2- DB9 2 3 5 7 8 10 9 2 74HC125 3 1 C1+ 16 0.1 F C1- C2+ 15 VTST V+ 2 V- 6 1 F + + 10 k 74HC125 5 6 4 PTA0 VSS VSSA VDD N.C. IRQ PTC3 N.C. VDD N.C. 9.8304 MHz CLOCK OSC2 OSC1 PTC0 N.C. VDDA VDD 0.1 F
PTC1
N.C.
Figure 19-11. Forced Monitor Mode (High)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 243
Development Support
VDD RST 0.1 F VDDA VDD 0.1 F N.C. 9.8304 MHz CLOCK MAX232 4 1 F + 5 4 1 F + 5 C2- DB9 2 3 5 7 8 10 9 74HC125 3 2 1 C1+ 16 0.1 F C1- C2+ 15 VTST V+ 2 V- 6 1 F + + 10 k 74HC125 5 6 4 VSS PTA0 VSSA VDD 9.1 V 1 k 2 k IRQ PTC1 PTC3 VDD OSC2 VDD OSC1 PTC0 10 k 10 k
Figure 19-12. Standard Monitor Mode Table 19-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode must be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If $FFFE and $FFFF does not contain $FF (programmed state): - The external clock is 4.9152 MHz with PTC3 low or 9.8304 MHz with PTC3 high - IRQ = VTST 2. If $FFFE and $FFFF contain $FF (erased state): - The external clock is 9.8304 MHz - IRQ = VDD (this can be implemented through the internal IRQ pullup) 3. If $FFFE and $FFFF contain $FF (erased state): - IRQ = VSS (ICG is selected, no external clock required) Once out of reset, the MCU waits for the host to send eight security bytes (see 19.3.2 Security). After the security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to receive a command. NOTE The PTA0 pin must remain high for 24 bus cycles after the RST pin goes high to enter monitor mode properly.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 244 Freescale Semiconductor
Monitor Module (MON)
Table 19-1. Monitor Mode Signal Requirements and Options
Serial Mode Selection Divider Reset Comm. ICG Vector PTA0 PTC0 PTC1 PTC3 X X $FFFF (blank) $FFFF (blank) Not $FFFF -- 1 1 1 1 1 X 0 0 X 0 1 X Communication Speed COP External Bus Clock Frequency 4.9152 MHz 9.8304 MHz 9.8304 MHz X 2.4576 MHz 2.4576 MHz 2.4576 MHz Nominal 2.4576 MHz X Baud Range 9600 9600 9600 Nominal 9600 X
Mode
IRQ
RST
Normal Monitor
VTST VTST VDD
VDD or VSS VDD or VSS VDD VDD VDD or VSS RST [4]
OFF Disabled OFF Disabled OFF Disabled
Forced Monitor
VSS VDD or VSS VTST [6]
1
X
X
X
ON Disabled
User MON08 Function [Pin No.]
X COM [8]
X MOD0 [12]
X MOD1 [14]
X DIV4 [16]
X
Enabled
X OSC1 [13]
--
--
--
--
1. PTA0 must have a pullup resistor to VDD in monitor mode. 2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus frequency / 256. 3. External clock is a 4.1952 MHz or 9.8304 MHz canned oscillator on OSC1. 4. X = don't care. 5. MON08 pin refers to P&E Microcomputer Systems' MONOUT-Cyclone 2 by 8-pin connector.
NC NC NC NC NC NC OSC1 VDD
1 3 5 7 9 11 13 15
2 4 6 8 10 12 14 16
GND RST IRQ PTA0 NC PTC0 PTC1 PTC3
19.3.1.1 Normal Monitor Mode When VTST is applied to IRQ and PTC3 is low upon monitor mode entry, the bus frequency is a divide-by-two of the input clock. If PTC3 is high with VTST applied to IRQ upon monitor mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTC3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied to IRQ. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 245
Development Support
If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to either IRQ or RST. This condition states that as long as VTST is maintained on the IRQ pin after entering monitor mode, or if VTST is applied to RST after the initial reset to get into monitor mode (when VTST was applied to IRQ), then the COP will be disabled. In the latter situation, after VTST is applied to the RST pin, VTST can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode. 19.3.1.2 Forced Monitor Mode If entering monitor mode without high voltage on IRQ (where applied voltage is either VDD or VSS), then all port C pin requirements and conditions, including the PTC3 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. If IRQ = VDD on monitor mode entry, an external oscillator of 9.8304 MHz is required for a 9600 baud rate. If IRQ = VSS on monitor mode entry, the ICG generates a 9600 baud rate using the trimmed ICG value in the ICGTR5 register. If the ICGTR5 register is blank, the baud rate will be a nominal 9600 baud which may not be adequate for standard PC serial communication. When forced monitor mode is entered, the COP is always disabled regardless of the state of IRQ or RST. NOTE If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial POR reset. Once the part has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to enter monitor mode. 19.3.1.3 Monitor Vectors In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. NOTE Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST low will not exit monitor mode in this situation. Table 19-2 summarizes the differences between user mode and monitor mode. Table 19-2. Mode Differences
Functions Modes User Monitor Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 246 Freescale Semiconductor
Monitor Module (MON)
19.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
START BIT NEXT START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT
Figure 19-13. Monitor Data Format 19.3.1.5 Break Signal A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 19-14. Break Transaction 19.3.1.6 Baud Rate The communication baud rate is controlled by the external clock or ICG upon entry into monitor mode. Table 19-1 lists external frequencies required to achieve a standard baud rate of 9600 bps. The effective baud rate is the bus frequency divided by 256. 19.3.1.7 Commands The monitor ROM firmware uses these commands: * * * * * * READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE Wait one bit time after each echo before sending the next byte.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 247
Development Support
FROM HOST
READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
4 ECHO
1
4
1
4
1
3, 2
4 RETURN
Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte.
Figure 19-15. Read Transaction
FROM HOST
WRITE 3 ECHO 1
WRITE 3
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
1
3
1
3
1
2, 3
Notes: 1 = Echo delay, approximately 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte.
Figure 19-16. Write Transaction A brief description of each monitor mode command is given in Table 19-3 through Table 19-7. Table 19-3. READ (Read Memory) Command
Description Operand Data Returned Opcode Read byte from memory 2-byte address in high-byte:low-byte order Returns contents of specified address $4A Command Sequence
SENT TO MONITOR
READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
ECHO
RETURN
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 248 Freescale Semiconductor
Monitor Module (MON)
Table 19-4. WRITE (Write Memory) Command
Description Operand Data Returned Opcode
FROM HOST
Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence
WRITE
WRITE
ADDRESS HIGH
ADDRESS
HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
ECHO
Table 19-5. IREAD (Indexed Read) Command
Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed None Returns contents of next two addresses $1A Command Sequence
FROM HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 19-6. READSP (Read Stack Pointer) Command
Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence
FROM HOST
READSP
READSP
SP HIGH
SP LOW
ECHO
RETURN
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 249
Development Support
Table 19-7. RUN (Run User Program) Command
Description Operand Data Returned Opcode Executes PULH and RTI instructions None None $28 Command Sequence
FROM HOST
RUN
RUN
ECHO
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.
SP HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 SP + 7
Figure 19-17. Stack Pointer at Monitor Mode Entry
19.3.2 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain user-defined data. NOTE Do not leave locations $FFF6-$FFFD blank. For security reasons, program locations $FFF6-$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. See Figure 19-18.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 250 Freescale Semiconductor
Monitor Module (MON)
Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE The MCU does not transmit a break character until after the host sends the eight security bytes.
VDD 4096 + 32 CGMXCLK CYCLES RST BYTE 1 BYTE 2 BYTE 8 COMMAND 1 BYTE 2 ECHO BYTE 8 ECHO 2 BREAK 4 1 COMMAND ECHO
FROM HOST PA0 5 FROM MCU 1 BYTE 1 ECHO 4 1
Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 4 = Wait 1 bit time before sending next byte 5 = Wait until the monitor ROM runs
Figure 19-18. Monitor Mode Entry Timing To determine whether the security code entered is correct, check to see if bit 6 of RAM address $40 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank).
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 251
Development Support
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 252 Freescale Semiconductor
Chapter 20 Electrical Specifications
20.1 Introduction
This section contains electrical and timing specifications.
20.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 20.5 5.0-V DC Electrical Characteristics for guaranteed operating conditions.
Characteristic(1) Supply voltage Input voltage Maximum current per pin excluding those specified below Maximum current for pins PTA5-PTA7, PTD4 Maximum current for pins PTC0-PTC4 Maximum current into VDD Maximum current out of VSS Storage temperature 1. Voltages referenced to VSS Symbol VDD VIn I IPTA5-PTA7 IPTC0-PTC4 Imvdd Imvss Tstg Value - 0.3 to + 6.0 VSS - 0.3 to VDD + 0.3 15 20 25 150 150 - 55 to +150 Unit V V mA mA mA mA mA C
NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIn and VOut be constrained to the range VSS (VIn or VOut) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD).
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 253
Electrical Specifications
20.3 Functional Operating Range
Characteristic Operating temperature range Operating voltage range Symbol TA VDD Value - 40 to +85 3.0 10% 5.0 10% Unit C V
20.4 Thermal Characteristics
Characteristic Thermal resistance 42-pin SDIP 44-pin QFP I/O pin power dissipation Power dissipation(1) Constant(2) Average junction temperature Symbol JA PI/O PD K TJ Value 60 95 User determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA) Unit C/W W W W/C C
1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 254 Freescale Semiconductor
5.0-V DC Electrical Characteristics
20.5 5.0-V DC Electrical Characteristics
Characteristic(1) Output high voltage (ILoad = -2.0 mA) all I/O pins (ILoad = -10.0 mA) all I/O pins (ILoad = -20.0 mA) pins PTC0-PTC4 only Maximum combined IOH for port C, port E, port PTD0-PTD3 Maximum combined IOH for port PTD4-PTD7, port A, port B Maximum total IOH for all port pins Output low voltage (ILoad = 1.6 mA) all I/O pins (ILoad = 10 mA) all I/O pins (ILoad = 20mA) pins PTC0-PTC4 only Maximum combined IOL for port C, port E, port PTD0-PTD3 Maximum combined IOL for port PTD4-PTD7, port A, port B Maximum total IOL for all port pins Input high voltage All ports, IRQ, RST, OSC1 Input low voltage All ports, IRQ, RST, OSC1 DC injection current, all ports(3) Total DC current injection (sum of all I/O ports Hi-Z leakage current(4) Input current Pullup resistors (as input only) Ports PTA7/KBD7-PTA0/KBD0, PTC6-PTC0, PTD7/T2CH1-PTD0/SS Capacitance Ports (as input or output) Monitor mode entry voltage Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage Low-voltage inhibit reset/recover hysteresis (VTRIPF + VHYS = VTRIPR) POR rearm voltage(5) POR reset voltage(6) rate(7) POR rise time ramp I/O)(3) Symbol VOH VOH VOH IOH1 IOH2 IOHT VOL VOL VOL IOL1 IOL2 IOLT VIH VIL IINJ IINJTOT IIL IIn RPU COut CIn VTST VTRIPF VTRIPR VHYS VPOR VPORRST RPOR Min VDD - 0.8 VDD - 1.5 VDD - 1.5 -- -- -- -- -- -- -- -- -- 0.7 x VDD VSS - 2.0 - 25 -- -- 20 -- -- VDD + 2.5 3.90 4.20 -- 0 0 0.035 Typ(2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 45 -- -- -- 4.25 4.35 100 -- 700 -- Max -- -- -- 50 50 100 0.4 1.5 1.5 50 50 100 VDD 0.2 x VDD + 2.0 +25 10 1 65 12 8 VDD + 4.0 4.50 4.60 -- 100 800 -- Unit V V V mA mA mA V V V mA mA mA V V mA mA A A k
pF V V V mV mV mV V/ms
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted 2. Typical values reflect average measurements at midpoint of voltage range, 25C only. 3. Some disturbance of the ADC accuracy is possible during any injection event and is dependent on board layout and power supply decoupling. This parameter is guaranteed by characterization. 4. Pullups and pulldowns are disabled. Port B leakage is specified in 20.16 ADC Characteristics. 5. Maximum is highest voltage that POR is guaranteed. 6. Maximum is highest voltage that POR is possible. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 255
Electrical Specifications
20.6 3.0-V DC Electrical Characteristics
Characteristic(1) Output high voltage (ILoad = -0.6 mA) all I/O pins (ILoad = -4.0 mA) all I/O pins (ILoad = -10.0 mA) pins PTC0-PTC4 only Maximum combined IOH for port C, port E, port PTD0-PTD3 Maximum combined IOH for port PTD4-PTD7, port A, port B Maximum total IOH for all port pins Output low voltage (ILoad = 0.5 mA) all I/O pins (ILoad = 5.0 mA) all I/O pins (ILoad = 10.0 mA) pins PTC0-PTC4 only Maximum combined IOL for port C, port E, port PTD0-PTD3 Maximum combined IOL for port PTD4-PTD7, port A, port B Maximum total IOL for all port pins Input high voltage All ports, IRQ, RST, OSC1 Input low voltage All ports, IRQ, RST, OSC1 DC injection current, all ports(3) Total DC current injection (sum of all I/O) I/O ports Hi-Z leakage current(4) Input current Pullup resistors (as input only) Ports PTA7/KBD7-PTA0/KBD0, PTC6-PTC0, PTD7/T2CH1-PTD0/SS Capacitance Ports (as input or output) Monitor mode entry voltage Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage Low-voltage inhibit reset/recover hysteresis (VTRIPF + VHYS = VTRIPR) POR rearm voltage(5) POR reset voltage
(6) (3)
Symbol VOH VOH VOH IOH1 IOH2 IOHT VOL VOL VOL IOL1 IOL2 IOLT VIH VIL IINJ IINJTOT IIL IIn RPU COut CIn VTST VTRIPF VTRIPR VHYS VPOR VPORRST RPOR
Min VDD - 0.3 VDD - 1.0 VDD -1.0 -- -- -- -- -- -- -- -- -- 0.7 x VDD VSS - 2.0 - 25 -- -- 20 -- -- VDD + 2.5 2.45 2.55 -- 0 0 0.02
Typ(2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 45 -- -- -- 2.60 2.66 60 -- 700 --
Max -- -- -- 30 30 60 0.3 1.0 1.0 30 30 60 VDD 0.3 x VDD + 2.0 +25 10 1 65 12 8 VDD + 4.0 2.70 2.80 -- 100 800 --
Unit V V V mA mA mA V V V mA mA mA V V mA mA A A k
pF V V V mV mV mV V/ms
POR rise time ramp rate(7)
1. VDD = 3.0 Vdc 10%, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted 2. Typical values reflect average measurements at midpoint of voltage range, 25C only. 3. Some disturbance of the ADC accuracy is possible during any injection event and is dependent on board layout and power supply decoupling. This parameter is guaranteed by characterization. 4. Pullups and pulldowns are disabled. 5. Maximum is highest voltage that POR is guaranteed. 6. Maximum is highest voltage that POR is possible. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 256 Freescale Semiconductor
Supply Current Characteristics
20.7 Supply Current Characteristics
Characteristic(1) Run mode VDD supply current(3) Wait mode VDD supply current(4) Stop mode VDD supply current(5) 25C 25C with TBM enabled(6) 25C with LVI and TBM enabled(6) -40C to 85C with TBM enabled(6) -40C to 85C with LVI and TBM enabled(6) Stop mode VDD supply current(5) 25C 25C with TBM enabled(6) 25C with LVI and TBM enabled(6) -40C to 85C with TBM enabled(6) -40C to 85C with LVI and TBM enabled(6) Voltage 5.0 3.0 5.0 3.0 Bus Frequency (MHz) 8 4 8 4 Symbol Typ(2) 15 4.5 4 1.5 1 20 300 50 500 2 12 200 30 300 Max 20 8 8 4 5 -- -- -- -- 3 -- -- -- -- Unit
RIDD WIDD
mA mA
5.0
SIDD
A
3.0
SIDD
A
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted 2. Typical values reflect average measurements at 25C only. 3. Run (operating) IDD measured using external square wave clock source (fOSC = 32 MHz for 5 V and fOSC = 16 MHz for 3 V). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOSC = 32 MHz for 5 V and fOSC = 16 MHz for 3 V). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs. Measured with ICG and LVI enabled. 5. Stop IDD is measured with OSC1 = VSS. 6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32 MHz for 5 V and fOSC = 16 MHz for 3 V).
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 257
Electrical Specifications
20.8 5-V Control Timing
Characteristic(1) Internal operating frequency Internal clock period (1/fOP) RST input pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period Symbol fOP (fBus) tcyc tRL tILIH tILIL Min -- 122 50 50 Note
(2)
Max 8 -- -- -- --
Unit MHz ns ns ns tcyc
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
tRL RST tILIL tILIH IRQ
Figure 20-1. RST and IRQ Timing
20.9 3-V Control Timing
Characteristic(1) Internal operating frequency Internal clock period (1/fOP) RST input pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period Symbol fOP (fBus) tcyc tRL tILIH tILIL Min -- 244 125 125 Note
(2)
Max 4 -- -- -- --
Unit MHz ns ns ns tcyc
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
tRL RST tILIL tILIH IRQ
Figure 20-2. RST and IRQ Timing
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 258 Freescale Semiconductor
Internal Oscillator Characteristics
20.10 Internal Oscillator Characteristics
Characteristic(1) Internal oscillator base frequency(2), (3) Internal oscillator tolerance Internal oscillator multiplier(4) Symbol fINTOSC fOSC_TOL N Min 230.4 -25 1 Typ 307.2 -- -- Max 384 +25 127 Unit kHz % --
1. VDD = 5.5 Vdc to 2.7 Vdc, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted 2. Internal oscillator is selectable through software for a maximum frequency. Actual frequency will be multiplier (N) x base frequency. 3. fBus = (fINTOSC / 4) x N when internal clock source selected 4. Multiplier must be chosen to limit the maximum bus frequency of 4 MHz for 2.7-V operation and 8 MHz for 4.5-V operation.
20.11 External Oscillator Characteristics
Characteristic(1) External clock With ICG clock disabled With ICG clock enabled EXTSLOW = 1(4) EXTSLOW = 0(4) External crystal options(7)(8) EXTSLOW = 1(4) EXTSLOW = 0(4) Crystal load capacitance(9) Crystal fixed capacitance(9) Crystal tuning capacitance(9)
(9)
Symbol
Min dc(5)
Typ -- -- -- -- -- -- 2 x CL 2 x CL 10 --
Max 32 M(6)
Unit
option(2)(3)
fEXTOSC 60 307.2 k fEXTOSC CL C1 C2 RB RS 30 k 1M -- -- -- -- -- 307.2 k 32 M(6) 100 k 10 M -- -- -- -- --
Hz
Hz pF pF pF M M
Feedback bias resistor Series resistor
(9)(10)
1. VDD = 5.5 to 2.7 Vdc, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted 2. Setting EXTCLKEN configuration option enables OSC1 pin for external clock square-wave input. 3. No more than 10% duty cycle deviation from 50% 4. EXTSLOW configuration option configures external oscillator for a slow speed crystal and sets the clock monitor circuits of the ICG module to expect an external clock frequency that is higher/lower than the internal oscillator base frequency, fINTOSC. 5. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this information. 6. MCU speed derates from 32 MHz at VDD = 4.5 Vdc to 16 MHz at VDD = 2.7 Vdc. 7. Setting EXTCLKEN and EXTXTALEN configuration options enables OSC1 and OSC2 pins for external crystal option. 8. fBus = (fEXTOSC / 4) when external clock source is selected. 9. Consult crystal vendor data sheet, see Figure 7-4. External Clock Generator Block Diagram. 10. Not required for high-frequency crystals
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 259
Electrical Specifications
20.12 Trimmed Accuracy of the Internal Clock Generator
The unadjusted frequency of the low-frequency base clock (IBASE), when the comparators in the frequency comparator indicate zero error, can vary as much as 25% due to process, temperature, and voltage. The trimming capability exists to compensate for process effects. The remaining variation in frequency is due to temperature, voltage, and change in target frequency (multiply register setting). These effects are designed to be minimal, however variation does occur. Better performance is seen at 3 V and lower settings of N.
20.12.1 2.7-Volt to 3.3-Volt Trimmed Internal Clock Generator Characteristics
Characteristic(1) Absolute trimmed internal oscillator tolerance(2), (3) -40C to 85C Variation over temperature(3), (4) Variation over voltage 25C -40C to 85C
(3), (5)
Symbol Fabs_tol Var_temp Var_volt
Min -- -- -- --
Typ 2.5 0.03 0.5 0.7
Max 4.0 0.05 2.0 2.0
Unit % %/C %/V
1. These specifications concern long-term frequency variation. Each measurement is taken over a 1-ms period. 2. Absolute value of variation in ICG output frequency, trimmed at nominal VDD and temperature, as temperature and VDD are allowed to vary for a single given setting of N. 3. Specification is characterized but not tested. 4. Variation in ICG output frequency for a fixed N and voltage 5. Variation in ICG output frequency for a fixed N
20.12.2 4.5-Volt to 5.5-Volt Trimmed Internal Clock Generator Characteristics
Characteristic(1) Absolute trimmed internal oscillator -40C to 85C Variation over temperature(3), (4) Variation over voltage(3), (5) 25C -40C to 85C tolerance(2), (3) Symbol Fabs_tol Var_temp Var_volt Min -- -- -- -- Typ 4.0 0.05 1.0 1.0 Max 4.0 0.08 2.0 2.0 Unit % %/C %/V
1. These specifications concern long-term frequency variation. Each measurement is taken over a 1-ms period. 2. Absolute value of variation in ICG output frequency, trimmed at nominal VDD and temperature, as temperature and VDD are allowed to vary for a single given setting of N. 3. Specification is characterized but not tested. 4. Variation in ICG output frequency for a fixed N and voltage 5. Variation in ICG output frequency for a fixed N
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 260 Freescale Semiconductor
Output High-Voltage Characteristics
20.13 Output High-Voltage Characteristics
0 -5 -10 -15 IOH (mA) -20 -25 -30 -35 -40 3 3.2 3.4 3.6 VOH (V) 3.8 4.0 4.2 -40 0 25 85
VOH > VDD -0.8 V @ IOH = -2.0 mA VOH > VDD -1.5 V @ IOH = -10.0 mA
Figure 20-3. Typical High-Side Driver Characteristics - Port PTA7-PTA0 (VDD = 4.5 Vdc)
0 -5 -10 -15 -20 -25 1.9 VOH (V) VOH > VDD -0.3 V @ IOH = -0.6 mA VOH > VDD -1.0 V @ IOH = -10.0 mA 1.3 1.5 1.7 2.1 2.3 2.5 -40 0 25 85
Figure 20-4. Typical High-Side Driver Characteristics - Port PTA7-PTA0 (VDD = 2.7 Vdc)
0 -5 -10 -15 IOH (mA) -20 -25 -30 -35 -40 3 3.2 3.4 3.6 VOH (V) 3.8 4.0 4.2 -40 0 25 85
Figure 20-5. Typical High-Side Driver Characteristics - Port PTC4-PTC0 (VDD = 4.5 Vdc)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 261
IOH (mA)
VOH > VDD -1.5 V @ IOH = -20.0 mA
Electrical Specifications
0 -5 -10 -15 -20 -25 1.9 VOH (V) VOH > VDD -1.0 V @ IOH = -10.0 mA 1.3 1.5 1.7 2.1 2.3 2.5 -40 0 25 85 IOH (mA) 0 -10 -20 -30 IOH (mA) -40 -50 -60 -70 -80 -90 3 3.2 3.4 3.6 VOH > VDD -0.8 V @ IOH = -2.0 mA VOH > VDD -1.5 V @ IOH = -10.0 mA 3.8 VOH (V) 4.0 4.2 4.4 4.6 -40 0 25 85
Figure 20-6. Typical High-Side Driver Characteristics - Port PTC4-PTC0 (VDD = 2.7 Vdc)
Figure 20-7. Typical High-Side Driver Characteristics - Ports PTB7-PTB0, PTC6-PTC5, PTD7-PTD0, and PTE1-PTE0 (VDD = 5.5 Vdc)
0 -5 -10 -15 -20 -25 1.9 VOH (V) VOH > VDD -0.3 V @ IOH = -0.6 mA VOH > VDD -1.0 V @ IOH = -4.0 mA 1.3 1.5 1.7 2.1 2.3 2.5 -40 0 25 85
Figure 20-8. Typical High-Side Driver Characteristics - Ports PTB7-PTB0, PTC6-PTC5, PTD7-PTD0, and PTE1-PTE0 (VDD = 2.7 Vdc)
IOH (mA)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 262 Freescale Semiconductor
Output Low-Voltage Characteristics
20.14 Output Low-Voltage Characteristics
35 30 25 IOL (mA) 20 15 10 5 0 0 0.2 0.4 0.6 0.8 VOL (V) 1.0 1.2 1.4 1.6 -40 0 25 85
VOL < 0.4 V @ IOL = 1.6 mA VOL < 1.5 V @ IOL = 10.0 mA
Figure 20-9. Typical Low-Side Driver Characteristics - Port PTA7-PTA0 (VDD = 5.5 Vdc)
14 12 10 IOL (mA) 8 6 4 2 0 0.2 0.4 0.6 0.8 1.0 VOL (V) 1.2 1.4 1.6 -40 0 25 85
VOL < 0.3 V @ IOL = 0.5 mA VOL < 1.0 V @ IOL = 6.0 mA
Figure 20-10. Typical Low-Side Driver Characteristics - Port PTA7-PTA0 (VDD = 2.7 Vdc)
60 50 IOL (mA) 40 30 20 10 0 0.4 0.6 0.8 VOL (V) VOL < 1.5 V @ IOL = 20 mA 1.0 1.2 1.4 1.6 -40 0 25 85
Figure 20-11. Typical Low-Side Driver Characteristics - Port PTC4-PTC0 (VDD = 4.5 Vdc)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 263
Electrical Specifications
30 25 20 IOL (mA) 15 10 5 0 0.2 0.4 0.6 0.8 1.0 VOL (V) 1.2 1.4 1.6 -40 0 25 85
VOL < 0.8 V @ IOL = 10 mA
Figure 20-12. Typical Low-Side Driver Characteristics - Port PTC4-PTC0 (VDD = 2.7 Vdc)
35 30 25 IOL (mA) 20 15 10 5 0 0 0.2 0.4 0.6 0.8 VOL (V) 1.0 1.2 1.4 1.6 -40 0 25 85
VOL < 0.4 V @ IOL = 1.6 mA VOL < 1.5 V @ IOL = 10.0 mA
Figure 20-13. Typical Low-Side Driver Characteristics - Ports PTB7-PTB0, PTC6-PTC5, PTD7-PTD0, and PTE1-PTE0 (VDD = 5.5 Vdc)
14 12 10 IOL (mA) 8 6 4 2 0 0 0.2 0.4 0.6 0.8 VOL (V) 1.0 1.2 1.4 1.6 -40 0 25 85
VOL < 0.3 V @ IOL = 0.5 mA VOL < 1.0 V @ IOL = 6.0 mA
Figure 20-14. Typical Low-Side Driver Characteristics - Ports PTB7-PTB0, PTC6-PTC5, PTD7-PTD0, and PTE1-PTE0 (VDD = 2.7 Vdc)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 264 Freescale Semiconductor
Typical Supply Currents
20.15 Typical Supply Currents
16 14 12 10 IDD (mA) 8 6 4 2 0 0 1 2 3 4 5 fBUS (MHz) 6 7 8 9 5.5 V 3.6 V
Figure 20-15. Typical Operating IDD, with All Modules Turned On (-40C to 85C)
5.0 4.5 4.0 3.5 3.0 IDD (mA) 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 4 fBUS (MHz) 5 6 7 8 5.5 V 3.6 V
Figure 20-16. Typical Wait Mode IDD, with all Modules Disabled (-40C to 85C)
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 265
Electrical Specifications
20.16 ADC Characteristics
Characteristic(1) Supply voltage Input voltages Resolution Absolute accuracy (VREFL = 0 V, VREFH = VDDA = 5 V 10%) ADC internal clock Conversion range Power-up time ADC voltage reference high ADC voltage reference low Conversion time Sample time
(2)
Symbol VDDA VADIN BAD AAD
Min 2.7 (VDD min) 0 8 --
Max 5.5 (VDD max) VDDA 8 1
Unit V V Bits LSB
Comments VDDA should be tied to the same potential as VDD via separate traces.
Includes quantization tAIC = 1/fADIC, tested only at 1 MHz VSSA VADIN VDDA VREFL VREFH VREFL VREFH
fADIC RAD tADPU VREFH VREFL tADC tADS ZADI FADI CADI --
0.5 VREFL 16 VSSA - 0.1 VSSA - 0.1 16 5 00 FE -- --
1.048 VREFH
MHz V tAIC cycles
VDDA + 0.1 VDDA + 0.1 17 -- 01 FF 8 1
V V tAIC cycles tAIC cycles Hex Hex pF A
Zero input reading(3) Full-scale reading(3)
VIN = VREFL VIN = VREFH Not tested
Input capacitance Input Port B leakage(4)
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, VDDA = 5.0 Vdc 10%, VSSA = 0 Vdc, VREFH = 5.0 Vdc 10%, VREFL = 0 2. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 4. The external system error caused by input leakage current is approximately equal to the product of R source and input current.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 266 Freescale Semiconductor
5.0-V SPI Characteristics
20.17 5.0-V SPI Characteristics
Diagram Number(1) Characteristic(2) Operating frequency Master Slave 1 2 3 4 Cycle time Master Slave Enable lead time Enable lag time Clock (SPSCK) high time Master Slave Clock (SPSCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time, slave(3) CPHA = 0 CPHA = 1 Disable time, slave(4) Data valid time, after enable edge Master Slave(5) Data hold time, outputs, after enable edge Master Slave Symbol Min Max Unit
fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(S) tLag(S) tSCKH(M) tSCKH(S) tSCKL(M) tSCKL(S) tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS(S) tV(M) tV(S) tHO(M) tHO(S)
fOP/128 dc 2 1 1 1 tCYC -25 1/2 tCYC -25 tCYC -25 1/2 tCYC -25 30 30 30 30 0 0 -- -- -- 0 0
fOP/2 fOP 128 -- -- -- 64 tCYC -- 64 tCYC -- -- -- -- -- 40 40 40 50 50 -- --
MHz MHz tCYC tCYC tCYC tCYC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5
6
7
8 9 10
11
1. Numbers refer to dimensions in Figure 20-17 and Figure 20-18. 2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 267
Electrical Specifications
20.18 3.0-V SPI Characteristics
Diagram Number(1) Characteristic(2) Operating frequency Master Slave 1 2 3 4 Cycle time Master Slave Enable lead time Enable lag time Clock (SPSCK) high time Master Slave Clock (SPSCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time, slave(3) CPHA = 0 CPHA = 1 Disable time, slave(4) Data valid time, after enable edge Master Slave(5) Data hold time, outputs, after enable edge Master Slave Symbol Min Max Unit
fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(s) tLag(s) tSCKH(M) tSCKH(S) tSCKL(M) tSCKL(S) tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS(S) tV(M) tV(S) tHO(M) tHO(S)
fOP/128 dc 2 1 1 1 tCYC -35 1/2 tCYC -35 tCYC -35 1/2 tCYC -35 40 40 40 40 0 0 -- -- -- 0 0
fOP/2 fOP 128 -- -- -- 64 tCYC -- 64 tCYC -- -- -- -- -- 50 50 50 60 60 -- --
MHz MHz tCYC tCYC tCYC tCYC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5
6
7
8 9 10
11
1. Numbers refer to dimensions in Figure 20-17 and Figure 20-18. 2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 268 Freescale Semiconductor
3.0-V SPI Characteristics
SS INPUT
SS PIN OF MASTER HELD HIGH 1
SPSCK OUTPUT CPOL = 0
NOTE
5 4
SPSCK OUTPUT CPOL = 1
NOTE
5 4 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT
MISO INPUT
MSB IN 11
BITS 6-1
MOSI OUTPUT
MASTER MSB OUT
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
a) SPI Master Timing (CPHA = 0)
SS INPUT
SS PIN OF MASTER HELD HIGH 1
SPSCK OUTPUT CPOL = 0
5 4
NOTE
SPSCK OUTPUT CPOL = 1
5 4 6 7 LSB IN 10 BITS 6-1 MASTER LSB OUT
NOTE
MISO INPUT 10 MOSI OUTPUT
MSB IN 11 MASTER MSB OUT
BITS 6-1
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 20-17. SPI Master Timing
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 269
Electrical Specifications
SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO INPUT SLAVE 6 MOSI OUTPUT MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN SLAVE LSB OUT 11 5 4 9 NOTE 5 4 3
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO OUTPUT 5 4 10 NOTE SLAVE 6 MOSI INPUT MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN 9 SLAVE LSB OUT 5 4 3
Note: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 20-18. SPI Slave Timing
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 270 Freescale Semiconductor
Timer Interface Module Characteristics
20.19 Timer Interface Module Characteristics
Characteristic Input capture pulse width Symbol tTIH, tTIL Min 1 Max -- Unit tCYC
20.20 Memory Characteristics
Characteristic RAM data retention voltage FLASH program bus clock frequency FLASH read bus clock frequency FLASH page erase time <1 k cycles >1 k cycles FLASH mass erase time FLASH PGM/ERASE to HVEN set up time FLASH high-voltage hold time FLASH high-voltage hold time (mass erase) FLASH program hold time FLASH program time FLASH return to read time FLASH cumulative program HV period FLASH program endurance(4) FLASH data retention time(5) Symbol VRDR -- fRead(1) tErase tMErase tNVS tNVH tNVHL tPGS tPROG tRCV(2) tHV(3) -- -- Min 1.3 1 8k 0.9 3.6 4 10 5 100 5 30 1 -- 10 k 15 Typ -- -- -- 1 4 -- -- -- -- -- -- -- -- 100k 100 Max -- -- 8M 1.1 5.5 -- -- -- -- -- 40 -- 4 -- -- Unit V MHz Hz ms ms s s s s s s ms Cycles Years
1. fRead is defined as the frequency range for which the FLASH memory can be read. 2. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to 0. 3. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) tHV maximum. 4. Typical endurance was evaluated for this product family. For additional information on how Freescale defines Typical Endurance, please refer to Engineering Bulletin EB619. 5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618.
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 271
Electrical Specifications
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 272 Freescale Semiconductor
Chapter 21 Ordering Information and Mechanical Specifications
21.1 Introduction
This section contains ordering numbers for the MC68HC908GT16 and MC68HC908GT8 and gives the dimensions for: * 42-pin shrink dual in-line package (case 858-01) * 44-pin plastic quad flat pack (case 824A-01) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Semiconductor sales office.
21.2 MC Order Numbers
Table 21-1. MC Order Numbers
MC Order Number MC908GT16CB MC908GT16CFB MC908GT8CB MC908GT8CFB Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package 42-pin SDIP 44-pin QFP 42-pin SDIP 44-pin QFP
MC908GTXX X XX
FAMILY PACKAGE DESIGNATOR TEMPERATURE RANGE
Figure 21-1. Device Numbering System
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 273
Ordering Information and Mechanical Specifications
21.3 42-Pin Shrink Dual in-Line Package (SDIP)
-A42 22 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
-B1 21
L C H
-TSEATING PLANE
F D 42 PL 0.25 (0.010)
M
G TA
S
N K J 42 PL 0.25 (0.010)
M
M TB
S
DIM A B C D F G H J K L M N
INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.032 0.046 0.070 BSC 0.300 BSC 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 5.08 3.94 0.56 0.36 1.17 0.81 1.778 BSC 7.62 BSC 0.38 0.20 3.43 2.92 15.24 BSC 15 0 1.02 0.51
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 274 Freescale Semiconductor
44-Pin Plastic Quad Flat Pack (QFP)
21.4 44-Pin Plastic Quad Flat Pack (QFP)
B L B
33 34
23 22 S
-A-, -B-, -DD D
S
DETAIL A F
BASE METAL
S
B 0.20 (0.008) M C A-B
0.05 (0.002) A-B
-AL
-B-
V
(0.008) M
H A-B
S
DETAIL A
44 1 11 12
0.20
J
N
D 0.20 (0.008) M C A-B SECTION B-B
S
D
S
-DA 0.20 (0.008) M C A-B 0.05 (0.002) A-B S 0.20 (0.008) M H A-B
S S
D
S
D M
S
DETAIL C
CE -CSEATING PLANE
-HH
DATUM PLANE
0.01 (0.004) G M
NOTES: 1. 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 2. CONTROLLING DIMENSION: MILLIMETER. 3. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MILLIMETERS DIM MIN MAX A 9.90 10.10 B 9.90 10.10 C 2.10 2.45 D 0.30 0.45 E 2.00 2.10 F 0.30 0.40 G 0.80 BSC H --0.25 J 0.13 0.23 K 0.65 0.95 L 8.00 REF M 5 10 N 0.13 0.17 Q 0 7 R 0.13 0.30 S 12.95 13.45 T 0.13 --U 0 --V 12.95 13.45 W 0.40 --X 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.012 0.018 0.079 0.083 0.012 0.016 0.031 BSC --- 0.010 0.005 0.009 0.026 0.037 0.315 REF 5 10 0.005 0.007 0 7 0.005 0.012 0.510 0.530 0.005 --0 --0.510 0.530 0.016 --0.063 REF
M T
DATUM PLANE
-H-
R
K W X DETAIL C
Q
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 Freescale Semiconductor 275
Ordering Information and Mechanical Specifications
MC68HC908GT16 * MC68HC908GT8 Data Sheet, Rev. 3 276 Freescale Semiconductor
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MC68HC908GT16 Rev. 3, 09/2004

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